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"Using Abstraction for Efficient Formal Verification of Pipelined ..."

Miroslav N. Velev (2006)

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DOI: 10.1109/ISQED.2006.142

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/isqed/Velev06
Miroslav N. Velev:
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. ISQED 2006: 51-56

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