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"Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp ..."

Guangyi Lu et al. (2018)

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DOI: 10.1109/ISCAS.2018.8350905

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-04

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Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang:
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS 2018: 1-5

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