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"FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, ..."

Ankit Wagle et al. (2018)

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DOI: 10.1109/FPL.2018.00051

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

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  - conf/fpl/WagleYDV18
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  persistent URL:
  - https://dblp.org/rec/conf/fpl/WagleYDV18
Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. FPL 2018: 256-259

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