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"Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits."

Zhengjie Li et al. (2019)

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DOI: 10.1145/3289602.3293955

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-17

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  dblp key:
  - conf/fpga/LiXZPWL19
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  - https://dblp.org/rec/conf/fpga/LiXZPWL19
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai:
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA 2019: 121

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