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"VHDL Synthesis Using Structured Modeling."

Joseph Lis, Daniel Gajski (1989)

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DOI: 10.1145/74382.74486

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - https://dblp.org/rec/conf/dac/LisG89
Joseph Lis, Daniel Gajski:
VHDL Synthesis Using Structured Modeling. DAC 1989: 606-609

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