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"FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization ..."

Jason Cong, Chang Wu (1997)

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DOI: 10.1145/266021.266309

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Jason Cong, Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC 1997: 644-649

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