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"A power-efficient FPGA accelerator: Systolic array with cache-coherent ..."

Megumi Ito, Moriyoshi Ohara (2016)

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DOI: 10.1109/COOLCHIPS.2016.7503681

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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  - https://dblp.org/rec/conf/coolchips/ItoO16
Megumi Ito, Moriyoshi Ohara:
A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. COOL Chips 2016: 1-3

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