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"A 40-nm low-power SRAM with multi-stage replica-bitline technique for ..."

Shigenobu Komatsu et al. (2009)

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DOI: 10.1109/CICC.2009.5280731

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704

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