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"Floorplan Optimization for Hierarchical VLSI Design."

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Chia-Pin R. Liu (2009)

Dagstuhl

Trier

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DOI: —

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type: Conference or Workshop Paper

metadata version: 2010-03-08

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  dblp key:
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  persistent URL:
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Chia-Pin R. Liu:
Floorplan Optimization for Hierarchical VLSI Design. CAINE 2009: 114-119

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last updated on 2010-03-08 17:19 CET by the dblp team

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