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"High Performance VLSI Architecture Design for H.264 CAVLC Decoder."

Mythri Alle, Jayanta Biswas, S. K. Nandy (2006)

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DOI: 10.1109/ASAP.2006.36

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Mythri Alle, Jayanta Biswas, S. K. Nandy:
High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322

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