default search action

combined dblp search
author search
venue search
publication search

ask others

"VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable ..."

S. K. Misra et al. (1998)

> Home

Details and statistics

DOI: 10.1109/ICVD.1998.646627

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/MisraKSMD98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/MisraKSMD98
S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein:
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. VLSI Design 1998: 326-329

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.