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Naoya Torii
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2020 – today
- 2022
- [j6]Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi:
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator. Int. J. Netw. Comput. 12(2): 372-386 (2022) - [c13]Kotaro Hayashi, Ryuichi Minagawa, Naoya Torii:
Side-channel attack on COSO-based TRNG to estimate output bits. CANDARW 2022: 302-308 - 2021
- [c12]Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi:
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator. CANDAR 2021: 189-195
2010 – 2019
- 2016
- [j5]Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto:
ASIC implementation of random number generators using SR latches and its evaluation. EURASIP J. Inf. Secur. 2016: 10 (2016) - [j4]Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto:
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(1): 118-129 (2016) - [c11]Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto:
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. TrustED@CCS 2016: 23-30 - [c10]Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto:
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. CANDAR 2016: 642-648 - 2015
- [j3]Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii:
A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. J. Cryptogr. Eng. 5(3): 187-199 (2015) - 2014
- [c9]Tetsuya Izu, Yumi Sakemi, Masahiko Takenaka, Naoya Torii:
A Spoofing Attack against a Cancelable Biometric Authentication Scheme. AINA 2014: 234-239 - [c8]Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii:
Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis. FedCSIS 2014: 911-918 - [c7]Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii:
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. IWSEC 2014: 158-173 - [i1]Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto:
Dynamic Behavior of RS latches using FIB processing and probe connection. IACR Cryptol. ePrint Arch. 2014: 870 (2014) - 2013
- [c6]Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii:
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. CARDIS 2013: 3-15 - 2012
- [j2]Naoya Torii:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(1): 1 (2012)
2000 – 2009
- 2005
- [j1]Shoichi Masui, Kenji Mukaida, Masahiko Takenaka, Naoya Torii:
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. IEICE Trans. Electron. 88-C(4): 576-581 (2005) - 2002
- [c5]Kouichi Itoh, Jun Yajima
, Masahiko Takenaka, Naoya Torii:
DPA Countermeasures by Improving the Window Method. CHES 2002: 303-317 - 2001
- [c4]Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima
The Block Cipher SC2000. FSE 2001: 312-327 - [c3]Kouichi Itoh, Masahiko Takenaka, Naoya Torii:
DPA Countermeasure Based on the "Masking Method". ICISC 2001: 440-456 - 2000
- [c2]Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka:
Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA. CHES 2000: 25-40
1990 – 1999
- 1999
- [c1]Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, Yasushi Kurihara:
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201. CHES 1999: 61-72
Coauthor Index
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