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Kazuhiko Terada
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2020 – today
- 2021
- [j3]Hiroyuki Uzawa, Kazuhiko Terada, Koyo Nitta:
A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation. IEICE Trans. Commun. 104-B(5): 481-489 (2021) - [j2]Kenji Tanaka, Yuki Arikawa, Tsuyoshi Ito, Kazutaka Morita, Naru Nemoto, Kazuhiko Terada, Junji Teramoto, Takeshi Sakamoto:
Distributed Deep Learning With GPU-FPGA Heterogeneous Computing. IEEE Micro 41(1): 15-22 (2021) - 2020
- [c5]Kenji Tanaka, Yuki Arikawa, Tsuyoshi Ito, Kazutaka Morita, Naru Nemoto, Fumiaki Miura, Kazuhiko Terada, Junji Teramoto, Takeshi Sakamoto:
Communication-Efficient Distributed Deep Learning with GPU-FPGA Heterogeneous Computing. Hot Interconnects 2020: 43-46
2010 – 2019
- 2015
- [c4]Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu:
High-speed sorted-table search scheme for network processing. APCC 2015: 616-620 - 2012
- [c3]Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano:
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL 2012: 639-642 - 2011
- [c2]Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Akihiko Miyazaki, Masami Urano, Tsugumichi Shibata:
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction. GLOBECOM 2011: 1-5
2000 – 2009
- 2005
- [j1]Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino:
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. 88-B(10): 3952-3961 (2005)
1990 – 1999
- 1998
- [c1]Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru:
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP 1998: 2673-2676
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