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Jiang Chau Wang
Person information
- affiliation: University of Sao Paulo, Brazil
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2020 – today
- 2021
- [c46]Carolina Teng
, Renan W. Achjian, Caio C. Braga, Marcelo Knörich Zuffo
Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA. LASCAS 2021: 1-4
2010 – 2019
- 2019
- [c45]Guilherme Apolinario Silva Novaes, Luiz Carlos Moreira, Wang Jiang Chau:
Mapping and Placement in NoC-based Reconfigurable Systems Using an Adaptive Tabu Search Algorithm. LASCAS 2019: 145-148 - [c44]Guilherme Apolinario Silva Novaes, Luiz Carlos Moreira, Wang Jiang Chau:
Exploring Tabu search based algorithms for mapping and placement in NoC-based reconfigurable systems. SBCCI 2019: 6 - 2018
- [c43]Jose Eduardo Chiarelli Bueno Filho
On TLM traffic accuracy: A multifractal perspective. LASCAS 2018: 1-4 - [c42]Vinicius Martins, Jerson Paulo Guex, Luciana Shiroma Montali, Jiang Chau Wang:
The functional verification of a satellite transponder. LASCAS 2018: 1-4 - 2017
- [c41]Vinicius Martins, Jiang Chau Wang
Mixed signal verification to avoid integration mismatch in complex SoCs. LATS 2017: 1-6 - [c40]Jose Eduardo Chiarelli Bueno Filho
Multifractal on-chip traffic generation under TLM. SoCC 2017: 68-73 - 2016
- [c39]Gustavo Patino Alvarez
Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation. FORMATS 2016: 177-194 - [c38]Jose Eduardo Chiarelli Bueno Filho
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. SoCC 2016: 41-46 - 2015
- [j8]Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. J. Electron. Test. 31(3): 255-273 (2015) - [j7]Jonas Gomes Filho, Marius Strum, Jiang Chau Wang
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Int. J. Reconfigurable Comput. 2015: 902925:1-902925:13 (2015) - [c37]Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. ARC 2015: 419-426 - [c36]Ernesto Villegas Castillo, Jiang Chau Wang
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost. LASCAS 2015: 1-4 - [c35]Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS 2015: 1-6 - 2014
- [c34]Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. LATW 2014: 1-6 - [c33]Ernesto Villegas Castillo
DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm. NOCS 2014: 190-191 - 2013
- [j6]Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electron. Test. 29(2): 223-236 (2013) - [c32]Martha Johanna Sepúlveda, Guy Gogniat
3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. GECCO (Companion) 2013: 167-168 - [c31]Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. IDT 2013: 1-6 - [c30]Jonas Gomes Filho, Marius Strum, Wang Jiang Chau
A strategy for mapping reconfigurable cores in NoCs. LASCAS 2013: 1-4 - [c29]Jorge González
Long range dependence in intrachip transaction level traffic. LASCAS 2013: 1-4 - [c28]Johanna Sepúlveda, Guy Gogniat
QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs. LASCAS 2013: 1-4 - [c27]Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Formal equivalence checking between high-level and RTL hardware designs. LATW 2013: 1-6 - [c26]Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang
PrOCov: Probabilistic output coverage model. LATW 2013: 1-6 - [c25]Jonas Gomes Filho, Jiang Chau Wang
Exploring the problems of placement and mapping in NoC-based reconfizurable systems. ReConFig 2013: 1-4 - [c24]Johanna Sepúlveda, Guy Gogniat
Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. SBCCI 2013: 1-6 - [c23]Johanna Sepúlveda, Guy Gogniat
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. SBCCI 2013: 1-6 - 2012
- [j5]Johanna Sepúlveda, Ricardo Pires
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfigurable Comput. 2012: 578363:1-578363:10 (2012) - [c22]Martha Johanna Sepúlveda, Jiang Chau Wang
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) 2012: 1449-1450 - [c21]Johanna Sepúlveda, Guy Gogniat
Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI 2012: 1-6 - [c20]Gustavo Patino Alvarez
Workload and task characterization based on operation modes timing analysis. SoCC 2012: 248-253 - 2011
- [j4]Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electron. Test. 27(4): 485-503 (2011) - [c19]Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau
Formally verifying an RTOS scheduling monitor IP core in embedded systems. LATW 2011: 1-6 - [c18]Johanna Sepúlveda, Guy Gogniat
Dynamic NoC-based architecture for MPSoC security implementation. SBCCI 2011: 197-202 - 2010
- [j3]Johanna Sepúlveda, Ricardo Pires
Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Trans. Comput. Sci. 10: 187-201 (2010) - [c17]Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau
Automatic generation of a parameter-domain-based functional input coverage model. LATW 2010: 1-6 - [c16]Johanna Sepúlveda, Marius Strum, Jiang Chau Wang
The LRD traffic impact on the NoC-based SoCs. SBCCI 2010: 97-102
2000 – 2009
- 2009
- [c15]Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN 2009: 1221-1228 - [c14]Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI 2009 - 2007
- [c13]Frederico De Faria, Marius Strum, Jiang Chau Wang:
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI 2007: 265-272 - 2005
- [c12]Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang:
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS 2005: 327-332 - [c11]John Esquiagola
A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL 2005: 148-152 - [c10]Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005: 56-61 - 2004
- [j2]Jiang Chau Wang
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electron. Test. 20(4): 333-344 (2004) - 2003
- [j1]Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. 43(2): 209-215 (2003) - 2002
- [c9]Wang Jiang Chau, Paulo Sérgio Cardoso, Marius Strum, Ricardo Pires:
A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications. LATW 2002: 61-63 - [c8]Wang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires:
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units. LATW 2002: 64-69 - 2001
- [c7]Duarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau:
Synthesis of Multi-Burst Controllers as Modified Huffman Machines. SBCCI 2001: 220-225 - 2000
- [c6]Jose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau:
Self Test Built-in Plan for Data-Path Functional Units. LATW 2000: 9-14 - [c5]Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha:
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. SBCCI 2000: 41-46
1990 – 1999
- 1999
- [c4]Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang:
Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI 1999: 473-484 - 1998
- [c3]Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang:
A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium 1998: 33- - [c2]José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau:
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. SBCCI 1998: 244-248 - 1995
- [c1]Jiang Chau Wang, Edward P. Stabler:
Collective Test Generation and Test Set Compaction. ISCAS 1995: 2008-2011
Coauthor Index
aka: Johanna Sepúlveda
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