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Jyh-Ting Lai
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2000 – 2009
- 2008
- [j5]Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu
:
Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme. J. Signal Process. Syst. 52(1): 59-73 (2008) - 2007
- [j4]Jyh-Ting Lai, An-Yeu Wu
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 236-240 (2007) - [j3]Jyh-Ting Lai, An-Yeu Wu
A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems. IEEE Trans. Veh. Technol. 56(6): 3791-3806 (2007) - [c4]Chun-Yuan Chu, Jyh-Ting Lai, An-Yeu Wu
Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems. SiPS 2007: 403-406 - 2006
- [c3]Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu
A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 165-170 - [c2]Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu
A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 171-176 - 2004
- [j2]Meng-Da Yang, An-Yeu Wu
Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 57-60 (2004) - [j1]Meng-Da Yang, An-Yeu Wu
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 218-226 (2004) - [c1]Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu:
1000BASE-T Gigabit Ethernet baseband DSP IC design. ISCAS (4) 2004: 401-404
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