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Wolfgang Schlecker
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2010 – 2019
- 2016
- [j3]Simran Singh, Mikko Valkama
, Michael Epp, Wolfgang Schlecker:
Digitally Enhanced Wideband I/Q Downconversion Receiver With 2-Channel Time-Interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(1): 29-33 (2016) - 2015
- [j2]Simran Singh, Mikko Valkama
Frequency Response Mismatch Analysis in Time-Interleaved Analog I/Q Processing and ADCs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 608-612 (2015) - [j1]Simran Singh, Lauri Anttila
Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2268-2279 (2015) - [c5]Markus Allén
Digital full-band linearization of wideband direct-conversion receiver for radar and communications applications. ACSSC 2015: 1361-1368 - [c4]Simran Singh, Michael Epp, Wolfgang Schlecker, Mikko Valkama
Low-complexity digital correction of 4-channel time-interleaved ADC frequency response mismatch using adaptive I/Q signal processing. GlobalSIP 2015: 250-254 - 2014
- [c3]Daniel Münch, Michael Paulitsch, Michael Honold, Wolfgang Schlecker, Andreas Herkersdorf:
Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems. DSD 2014: 303-311
2000 – 2009
- 2005
- [c2]Oliver A. Pfänder, Christophe Layer
An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis. EDUTECH 2005: 121-131 - 2002
- [c1]Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer:
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. FPL 2002: 1097-1100
Coauthor Index
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