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Hang-Ting Lue
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2020 – today
- 2024
- [c13]Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. IMW 2024: 1-4 - [c12]Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F2 DRAM Below Equivalent 10nm Node. IMW 2024: 1-4 - [c11]Pei-Ci Jhang, Chi-Pin Lu, Jung-Yu Shieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Hang-Ting Lue, Pei-Ying Du, Chih-Yuan Lu:
Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide. IRPS 2024: 24 - 2023
- [c10]Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. IMW 2023: 1-4 - [c9]Chih-Chang Hsieh, Hang-Ting Lue, Yung-Chun Li, Shuo-Nan Hung, Chun-Hsiung Hung, Keh-Chung Wang, Chih-Yuan Lu:
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c8]Cheng-Lin Sung, Sheng-Ting Fan, Hang-Ting Lue, Wei-Chen Chen, Pei-Ying Du, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu:
First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures. IRPS 2022: 7 - 2021
- [c7]Hang-Ting Lue, Tzu-Hsuan Hsu, Cheng-Lin Sung, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu:
Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. IMW 2021: 1-4 - [c6]Cheng-Lin Sung, Hang-Ting Lue, Wei-Chen Chen, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. IMW 2021: 1-4 - [c5]Ming-Liang Wei
, Hussam Amrouch
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. IRPS 2021: 1-8 - [c4]Hang-Ting Lue, Han-Wen Hu
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. ISCAS 2021: 1-4 - 2020
- [c3]Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS 2020: 1-6 - [c2]Hang-Ting Lue
Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper). IRPS 2020: 1-6
2010 – 2019
- 2015
- [j3]Chun-Hsiung Hung, Meng-Fan Chang, Yih-Shan Yang, Yao-Jen Kuo, Tzu-Neng Lai, Shin-Jang Shen, Jo-Yu Hsu, Shuo-Nan Hung, Hang-Ting Lue
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. IEEE J. Solid State Circuits 50(6): 1491-1501 (2015) - 2014
- [c1]Yu-Ming Chang, Yuan-Hao Chang, Jian-Jia Chen
On Trading Wear-leveling with Heal-leveling. DAC 2014: 83:1-83:6 - 2011
- [j2]Chihyuan Lu, Hang-Ting Lue
State-of-the-art flash memory devices and post-flash emerging memories. Sci. China Inf. Sci. 54(5): 1039-1060 (2011)
2000 – 2009
- 2002
- [j1]Hang-Ting Lue
Microwave penetration depth measurement for high Tc superconductors by dielectric resonators. IEEE Trans. Instrum. Meas. 51(3): 433-439 (2002)
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