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Nathalie Julien
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Journal Articles
- 2011
- [j8]Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel:
Power/Energy Estimator for Designing WSN Nodes with Ambient Energy Harvesting Feature. EURASIP J. Embed. Syst. 2011 (2011) - 2008
- [j7]Antoine Courtay, Olivier Sentieys
, Johann Laurent, Nathalie Julien:
High-Level Interconnect Delay and Power Estimation. J. Low Power Electron. 4(1): 21-33 (2008) - [j6]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques 27(1-2): 235-254 (2008) - 2007
- [j5]Johann Laurent, Eric Senn, Nathalie Julien:
Méthodes et outils d'estimation de la consommation de code embarqué sur processeur. Tech. Sci. Informatiques 26(5): 509-534 (2007) - 2005
- [j4]Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. EURASIP J. Adv. Signal Process. 2005(16): 2641-2654 (2005) - 2004
- [j3]Nathalie Julien:
Panorama des outils d'analyse et d'optimisation de la consommation dans les systèmes sur puce (SoC). Ann. des Télécommunications 59(7-8): 903-937 (2004) - 2003
- [j2]Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin:
Power Consumption Modeling and Characterization of the TI C6201. IEEE Micro 23(5): 40-49 (2003) - [j1]Nathalie Julien, S. Gailhard, Eric Martin:
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. J. VLSI Signal Process. 35(2): 195-211 (2003)
Conference and Workshop Papers
- 2024
- [c29]Naomi Kamoise
Comparing prospective methods to identify latent needs. ECCE 2024: 27:1-27:4 - [c28]Fanny Guennoc
Integrating ergonomics into the early stages of Digital Twin design: From the design of a Digital Twin for short-distance dairy producers to the definition of a generic and tool-based method. ECCE 2024: 28:1-28:7 - 2023
- [c27]Fatemeh Taei, Mohammed Adel Hamzaoui, Nathalie Julien:
CODIT 2023 Modeling of Smart Batteries for the Realization of a Digital Twin Prototype. CoDIT 2023: 2396-2401 - [c26]Aurélian Houé, Cédric Seguin, Florent Frizon de Lamotte, Nathalie Julien, Willy Allègre:
Modular and Distributed Architecture Using an Embedded Digital Twin for Adaptation of Assistive Technologies. SOHOMA 2023: 26-37 - [c25]Abbas Ramadan, Florent Frizon de Lamotte, Nathalie Julien:
Digital Twin Architecture for Ambient Assisted Living. SOHOMA 2023: 124-134 - 2022
- [c24]Nathalie Julien, Mohammed Adel Hamzaoui:
Integrating Lean Data and Digital Sobriety in Digital Twins Through Dynamic Accuracy Management. SOHOMA 2022: 107-117 - 2021
- [c23]Nathalie Julien, Eric Martin:
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. SOHOMA 2021: 161-172 - 2012
- [c22]Van-Trinh Hoang, Nathalie Julien, Pascal Berruet:
Design under constraints of availability and energy for sensor node in wireless sensor network. DASIP 2012: 1-8 - 2011
- [c21]Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel:
Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks. PATMOS 2011: 122-132 - 2010
- [c20]Ludovic Barrandon, Thierry Capitaine, Loïc Lagadec, Nathalie Julien, Christophe Moy, Thierry Monédière:
Virtual SoPC rad-hardening for satellite applications. ReCoSoC 2010: 179-180 - 2009
- [c19]Eric Senn, David Monnereau, André Rossi
Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. DSD 2009: 217-220 - 2008
- [c18]Antoine Courtay, Johann Laurent, Olivier Sentieys
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. PATMOS 2008: 359-368 - 2006
- [c17]David Elléouet, Nathalie Julien, Dominique Houzet:
A high level SoC power estimation based on IP modeling. IPDPS 2006 - [c16]David Elléouet, Yannig Savary, Nathalie Julien:
An FPGA Power Aware Design Flow. PATMOS 2006: 415-424 - [c15]Eric Senn, Nathalie Julien, David Elléouet, Yannig Savary, Nabil Abdelli:
Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design. ReCoSoC 2006: 83-90 - 2005
- [c14]Nathalie Julien, Johann Laurent, Eric Senn, David Elléouet, Yannig Savary, Nabil Abdelli, Jalei Ktari:
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling. ReCoSoC 2005: 137-142 - 2004
- [c13]Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin:
Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47 - [c12]Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin:
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. DATE 2004: 666-667 - [c11]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95 - [c10]Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin:
A Complete Methodology for Memory Optimization in DSP Applications. DSD 2004: 98-103 - [c9]David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin:
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD 2004: 394-401 - [c8]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI 2004: 82-85 - [c7]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280 - [c6]Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. PATMOS 2004: 342-351 - 2002
- [c5]Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin:
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. ISHPC 2002: 354-360 - [c4]Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin:
Power Consumption Estimation of a C Program for Data-Intensive Applications. PATMOS 2002: 332-341 - 1999
- [c3]S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. Great Lakes Symposium on VLSI 1999: 334-335 - 1998
- [c2]Stephane Gailhard, Nathalie Julien, Eric Martin:
Adaptive filters implementation performances under power dissipation constraint. EUSIPCO 1998: 1-4 - [c1]S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin:
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. Great Lakes Symposium on VLSI 1998: 426-
Informal and Other Publications
- 2006
- [i3]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power. CoRR abs/cs/0605142 (2006) - [i2]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
A Memory Aware High Level Synthesis Too. CoRR abs/cs/0605144 (2006) - [i1]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware High-Level Synthesis for Embedded Systems. CoRR abs/cs/0605145 (2006)
Coauthor Index
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