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Madhav P. Desai
Person information
- affiliation: Indian Institute of Technology Bombay, Mumbai, India
- affiliation (PhD): University of Illinois at Urbana-Champaign, Urbana, IL, USA
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2020 – today
- 2023
- [i11]Madhav P. Desai:
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache. CoRR abs/2305.17773 (2023) - 2022
- [c28]Neha V. Karanjkar, Madhav P. Desai:
Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration. SIMULTECH 2022: 142-150 - 2021
- [i10]Madhav P. Desai, Aniket Anand Deshmukh:
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches. CoRR abs/2108.00444 (2021)
2010 – 2019
- 2018
- [j7]Nanditha P. Rao, Madhav P. Desai:
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. Microelectron. J. 72: 86-99 (2018) - 2017
- [i9]Nanditha P. Rao, Madhav P. Desai:
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. CoRR abs/1706.03315 (2017) - 2016
- [c27]Kartik Lakhotia, Gabriel Caffarena
, Alberto Gil
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array. IWBBIO 2016: 266-276 - [i8]Madhav P. Desai, Virendra Sule:
Projective cofactor decompositions of Boolean functions and the satisfiability problem. CoRR abs/1603.04569 (2016) - [i7]Neha V. Karanjkar, Madhav P. Desai:
On Continuous-space Embedding of Discrete-parameter Queuing Systems. CoRR abs/1606.02900 (2016) - [i6]Nanditha P. Rao, Madhav P. Desai:
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. CoRR abs/1612.08239 (2016) - 2015
- [c26]Nanditha P. Rao, Madhav P. Desai:
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. DSD 2015: 714-721 - [c25]Neha V. Karanjkar, Madhav P. Desai:
An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique. MASCOTS 2015: 85-88 - 2014
- [i5]Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai:
On the likelihood of multiple bit upsets in logic circuits. CoRR abs/1401.1003 (2014) - [i4]Madhav P. Desai:
Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware. CoRR abs/1411.0863 (2014) - [i3]Neha V. Karanjkar, Madhav P. Desai:
Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique. CoRR abs/1411.2222 (2014) - [i2]Madhav P. Desai, Virendra Sule:
Generalized cofactors and decomposition of Boolean satisfiability problems. CoRR abs/1412.2341 (2014) - 2012
- [c24]Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai:
The Click2NetFPGA Toolchain. USENIX ATC 2012: 77-88 - 2010
- [c23]Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai:
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. DSD 2010: 147-154 - [c22]Gautam Hazari, Madhav P. Desai, G. Srinivas:
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. VLSI Design 2010: 15-20 - [i1]Madhav P. Desai:
On Cycles in Random Graphs. CoRR abs/1009.6046 (2010)
2000 – 2009
- 2009
- [c21]Pratyush Kumar, Madhav P. Desai:
Learning based address mapping for improving the performance of memory subsystems. MASCOTS 2009: 1-9 - 2007
- [c20]Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai:
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. VLSI Design 2007: 245-250 - [c19]Gautam Hazari, Madhav P. Desai, H. Kasture:
On the Impact of Address Space Assignment on Performance in Systems-on-Chip. VLSI Design 2007: 540-545 - [c18]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Parallelization of DC Analysis through Multiport Decomposition. VLSI Design 2007: 863-868 - 2006
- [c17]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design 2006: 695-700 - 2005
- [c16]Shabbir H. Batterywala, Madhav P. Desai:
Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90 - [c15]Madhav P. Desai, D. Manjunath:
On Range Matrices and Wireless Networks in d Dimensions. WiOpt 2005: 190-196 - 2004
- [c14]Vani Prasad, Madhav P. Desai:
On Buffering Schemes for Long Multi-Layer Nets. VLSI Design 2004: 455- - [c13]Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. VLSI Design 2004: 565-570 - [c12]Aditya Mittal, Madhav P. Desai:
A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. VLSI Design 2004: 571- - 2003
- [j6]Madhav P. Desai, H. Narayanan, Sachin B. Patkar:
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. Discret. Appl. Math. 131(2): 299-310 (2003) - [j5]Madhav P. Desai, Ritu Gupta, Abhay Karandikar, Kshitiz Saxena, Vinayak Samant:
Reconfigurable finite-state machine based IP lookup engine for high-speed router. IEEE J. Sel. Areas Commun. 21(4): 501-512 (2003) - [c11]Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design 2003: 99-104 - [c10]Vani Prasad, Madhav P. Desai:
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. VLSI Design 2003: 417-422 - 2002
- [j4]Madhav P. Desai, D. Manjunath:
On the connectivity in finite ad hoc networks. IEEE Commun. Lett. 6(10): 437-439 (2002) - [c9]Maryam Shojaei Baghini, Madhav P. Desai:
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. ASP-DAC/VLSI Design 2002: 317- - 2001
- [j3]Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao
Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectron. Reliab. 41(7): 1045-1048 (2001) - [c8]Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design 2001: 479- - [c7]Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai:
An On-Chip Coupling Capacitance Measurement Technique. VLSI Design 2001: 495-499 - 2000
- [c6]Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal:
Inductance Characterization of Small Interconnects Using Test-Signal Method. VLSI Design 2000: 376-
1990 – 1999
- 1999
- [c5]Rupesh S. Shelar, Madhav P. Desai, H. Narayanan:
Decomposition of Finite State Machines for Area, Delay Minimization. ICCD 1999: 620-625 - [c4]B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai:
A State Assignment Scheme Targeting Performance and Area. VLSI Design 1999: 378-383 - 1998
- [c3]Nevine Nassif, Madhav P. Desai, Dale H. Hall:
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. DAC 1998: 230-235 - 1996
- [c2]Madhav P. Desai, Yao-Tsung Yen:
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. DAC 1996: 125-130 - [c1]Madhav P. Desai, Radenko Cvijetic, James Jensen:
Sizing of Clock Distribution Networks for High Performance CPU Chips. DAC 1996: 389-394 - 1994
- [j2]Madhav P. Desai, Vasant B. Rao:
A characterization of the smallest eigenvalue of a graph. J. Graph Theory 18(2): 181-194 (1994) - 1993
- [j1]Madhav P. Desai, Vasant B. Rao:
On the Convergence of Reversible Markov Chains. SIAM J. Matrix Anal. Appl. 14(4): 950-966 (1993)
Coauthor Index
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