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Saman Sadr
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2010 – 2019
- 2018
- [c6]Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr:
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. ISSCC 2018: 106-108 - 2017
- [c5]Mohammad Sadegh Jalali, Masum Hossain, Kenneth Dyer, Saman Sadr:
High speed ADCs for wireline applications. MWSCAS 2017: 579-582 - 2014
- [j1]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye, Saman Sadr:
New 2-D Eye-Opening Monitor for Gb/s Serial Links. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1209-1218 (2014) - [c4]Roberto DiCecco, Roman Pahuta, Chris D. Holdenried, Saman Sadr:
Test considerations for jitter tolerance of wireline receivers. CCECE 2014: 1-5 - [c3]Chris D. Holdenried, Ryan Bespalko, Marcus van Ierssel, Mehrdad Ramezani, David Cassan, Siamak Sarvari, Saman Sadr:
Performance of edge tap decision feedback equalization methods for wireline receivers. NEWCAS 2014: 5-8 - 2012
- [c2]Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr:
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. ESSCIRC 2012: 225-228 - 2011
- [c1]Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr:
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. ISSCC 2011: 352-354
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