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Bishnu Prasad Das
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2020 – today
- 2024
- [j14]Prasanna Kumar Saragada, Bishnu Prasad Das
:
Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4586-4596 (2024) - [c24]Amandeep Singh, Bishnu Prasad Das:
PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks. ISCAS 2024: 1-5 - [c23]Sidharth Thomas, Jaskirat Singh Virdi, Anshul Verma, Bishnu Prasad Das, Kenichi Okada, Pratap Narayan Singh:
A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. ISCAS 2024: 1-5 - [c22]Anshul Verma
A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter. VLSID 2024: 156-161 - 2023
- [j13]Anu Verma
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1167-1177 (2023) - [c21]Amandeep Singh, Bishnu Prasad Das:
Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator. iSES 2023: 121-126 - [c20]Apurba Prasad Padhy, Bishnu Prasad Das:
Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application. VLSID 2023: 7-12 - [c19]Aditya Ramkumar, Anshul Verma
Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases. VLSID 2023: 92-97 - 2022
- [j12]Prasanna Kumar Saragada
In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1473-1483 (2022) - [c18]Anu Verma, Priyamvada Sharma, Bishnu Prasad Das:
RISC-V Core with Approximate Multiplier for Error-Tolerant Applications. DSD 2022: 239-246 - [c17]Anshul Verma
Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications. VDAT 2022: 185-198 - [c16]Aranya Gupta
Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks. VDAT 2022: 234-248
2010 – 2019
- 2019
- [j11]Priyamvada Sharma, Poorvi Jain, Bishnu Prasad Das:
An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications. Microelectron. J. 92 (2019) - [c15]Prasanna Kumar Saragada
An In-Memory Architecture for Machine Learning Classifier Using Logistic Regression. iSES 2019: 209-214 - [c14]Sumit Satyavijay Wadkar, Bishnu Prasad Das, Pramod Kumar Meher:
Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series. iSES 2019: 312-315 - [c13]Priyamvada Sharma
A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs. VDAT 2019: 371-382 - 2018
- [j10]Govinda Sannena, Bishnu Prasad Das:
Metastability immune and area efficient error masking flip-flop for timing error resilient designs. Integr. 61: 101-113 (2018) - [j9]Govinda Sannena
Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1223-1232 (2018) - 2017
- [c12]Swaati, Bishnu Prasad Das:
A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications. VDAT 2017: 487-495 - [c11]Poorvi Jain, Bishnu Prasad Das:
Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator. VLSID 2017: 315-320 - 2016
- [c10]Govinda Sannena, Bishnu Prasad Das:
A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance. ACM Great Lakes Symposium on VLSI 2016: 151-156 - [c9]Govinda Sannena, Bishnu Prasad Das:
Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application. iNIS 2016: 244-249 - 2014
- [j8]Bishnu Prasad Das, Hidetoshi Onodera:
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 183-187 (2014) - [j7]Bishnu Prasad Das, Hidetoshi Onodera:
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2535-2548 (2014) - [c8]Kaushik Vaidyanathan, Bishnu Prasad Das, Larry T. Pileggi:
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack. DAC 2014: 156:1-156:6 - [c7]Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - 2013
- [j6]Claire Palmer
Generating rules from data mining for collaboration moderator services. J. Intell. Manuf. 24(2): 313-330 (2013) - 2012
- [j5]Bishnu Prasad Das, Hidetoshi Onodera:
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation. IET Circuits Devices Syst. 6(6): 429-436 (2012) - [j4]Rahul Swarnkar, Alok Kumar Choudhary, Jenny A. Harding, Bishnu Prasad Das, Robert I. M. Young:
A framework for collaboration moderator services to support knowledge based collaboration. J. Intell. Manuf. 23(5): 2003-2023 (2012) - [c6]Rahul Swarnkar, Jennifer A. Harding, Bishnu Prasad Das, Robert I. M. Young, Sri Krishna Kumar:
Application of Collaboration Moderator Service in Pharmaceutical Industry: A Collaborative Drug Discovery Use Case. I-ESA 2012: 15-24 - 2010
- [c5]Bishnu Prasad Das, Hidetoshi Onodera:
Warning Prediction Sequential for Transient Error Prevention. DFT 2010: 382-390 - [c4]Alok Kumar Choudhary, Jenny A. Harding, Rahul Swarnkar, Bishnu Prasad Das, Robert I. M. Young:
Learning Collaboration Moderator Services: Supporting Knowledge Based Collaboration. PRO-VE 2010: 593-600
2000 – 2009
- 2008
- [c3]Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan:
Within-die gate delay variability measurement using re-configurable ring oscillator. CICC 2008: 133-136 - [c2]Janakiraman Viraraghavan
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672 - [c1]Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind:
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691 - 2007
- [j3]Bishnu Prasad Das, Anne-Françoise Cutting-Decelle
Towards the understanding of the requirements of a communication language to support process interoperation in cross-disciplinary supply chains. Int. J. Comput. Integr. Manuf. 20(4): 396-410 (2007) - [j2]Anne-Françoise Cutting-Decelle, Bob Young, Bishnu Prasad Das, Keith Case, Shahin Rahimifard, Chimay J. Anumba, Dino Bouchlaghem:
A review of approaches to supply chain communications: from manufacturing to construction. J. Inf. Technol. Constr. 12: 73-102 (2007) - 2006
- [j1]Anne-Françoise Cutting-Decelle, Bishnu Prasad Das, Robert I. M. Young, Keith Case, Shahin Rahimifard, Chimay J. Anumba, N. M. Bouchlaghem:
Building supply chain communication systems: a review of methods and techniques. Data Sci. J. 5: 29-51 (2006)
Coauthor Index
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