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Cao Liang
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2020 – today
- 2021
- [c6]Xiao Yu, Cao Liang, Hongyuan Wang, Suolan Liu, Yan Hui:
Unsupervised Video-based Person Re-identification Based on The Joint Global-local Metrics. CCIS 2021: 176-182 - [i1]Kaiwen Long, Chong Xing, Yuebin Qi, Pei Zhang, Changsong Wu, Wenxiao Fang, Jing Tan, Jie Chen, Shiming Zhang, Zuosheng Wang, Zuanmin Liu, Cao Liang, Jiaxiang Xu:
GearV: A Two-Gear Hypervisor for Mixed-Criticality IoT Systems. CoRR abs/2106.04514 (2021)
2010 – 2019
- 2018
- [j5]Cao Liang, Jingchun Feng, Ren Yuan:
Risk Evaluation of EPC Supply Chain Based on SCOR and Multi-Level Grey Model: A Case Study of China's Waste Incineration Plant Project. Int. J. Inf. Syst. Supply Chain Manag. 11(2): 54-76 (2018) - 2010
- [j4]Cao Liang, Xinming Huang:
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture. IEICE Trans. Electron. 93-C(3): 407-415 (2010)
2000 – 2009
- 2009
- [j3]Cao Liang, Xinming Huang:
SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications. EURASIP J. Embed. Syst. 2009 (2009) - [c5]Cao Liang, Xinming Huang:
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture. ASAP 2009: 231-234 - 2008
- [j2]Wenxuan Guo, Xinming Huang, Wenjing Lou, Cao Liang:
On Relay Node Placement and Assignment for Two-tiered Wireless Networks. Mob. Networks Appl. 13(1-2): 186-197 (2008) - [j1]Xinming Huang, Cao Liang, Jing Ma:
System Architecture and Implementation of MIMO Sphere Decoders on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 188-197 (2008) - [c4]Cao Liang, Xinming Huang:
SmartCell: A power-efficient reconfigurable architecture for data streaming applications. SiPS 2008: 257-262 - 2007
- [c3]Cao Liang, Xinming Huang, Jing Deng:
A fault tolerant and energy efficient routing protocol for urban sensor networks. Infoscale 2007: 27 - 2006
- [c2]Cao Liang, Jing Ma, Xinming Huang:
An FPGA based Co-Design Architecture for MIMO Lattice Decoders. ERSA 2006: 103-109 - [c1]Cao Liang, Jing Ma, Xinming Huang:
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms. FCCM 2006: 339-340
Coauthor Index
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