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Kishore K. Duganapalli
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2010 – 2019
- 2016
- [b1]Kishore K. Duganapalli:
Modelling and Test Generation for Crosstalk Faults in DSM Chips (Modellierung und Testfallgenerierung für Übersprechenfehler in DSM Chips). Bremen University, Germany, 2016 - [j2]Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier:
Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. J. Circuits Syst. Comput. 25(3): 1640018:1-1640018:14 (2016) - 2015
- [c5]Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier:
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. DDECS 2015: 3-8
2000 – 2009
- 2008
- [j1]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Crosstalk fault modeling in defective pair of interconnects. Integr. 41(1): 27-37 (2008) - 2007
- [c4]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS 2007: 161-164 - [i1]Shyam Praveen Vudathu, Kishore K. Duganapalli, Rainer Laur, D. Kubalinska, Angelika Bunse-Gerstner:
Parametric Yield Analysis of Mems via Statistical Methods. CoRR abs/0711.3287 (2007) - 2006
- [c3]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT 2006: 336-344 - [c2]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Modeling of Crosstalk Fault in Defective Interconnects. PATMOS 2006: 340-349 - 2005
- [c1]Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27
Coauthor Index
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