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Bartomeu Alorda
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2020 – today
- 2024
- [i1]Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura:
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR abs/2402.10917 (2024) - 2022
- [c29]Abdel Alheyasat, Gabriel Torrens
, Sebastià A. Bota, Bartomeu Alorda:
SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications. DCIS 2022: 1-6 - 2020
- [c28]Abdel Alheyasat, Gabriel Torrens
Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric. DCIS 2020: 1-6 - [c27]Andreu Moià-Pol, Pere Rullan, Bartomeu Alorda:
Intelligent Thermal Storage in the Balearic Islands Hotels with Solar Energy. Intelligent Environments (Workshops) 2020: 252-258 - [c26]Cristian Carmona, Juan Muñoz, Bartomeu Alorda:
New Approach to Indoor Thermal Climate Control Using Natural Building Envelope and Cross Ventilation Techniques. Intelligent Environments (Workshops) 2020: 259-267 - [c25]Abdel Alheyasat, Gabriel Torrens, Sebastià A. Bota, Bartomeu Alorda:
Bit-Cell Selection Analysis for Embedded SRAM-Based PUF. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j8]Gabriel Torrens
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7(3): 447-455 (2019) - [c24]Abdel Alheyasat, Gabriel Torrens
Weak and Strong SRAM cells analysis in embedded memories for PUF applications. DCIS 2019: 1-6 - [c23]Bartomeu Alorda, Cristian Carmona, Juan Muñoz, Francesc Masdeu, Gabriel Horrach:
Overheating Mitigation Strategies Analysis: A Mediterranean Case Study. Intelligent Environments (Workshops) 2019: 89-97 - [c22]Andreu Moià-Pol, Pere Rullan, Bartomeu Alorda:
Intelligent Energy Consumption in the Balearic Islands Hotels. Intelligent Environments (Workshops) 2019: 98-105 - 2017
- [c21]Bartomeu Alorda
Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift. DTIS 2017: 1-6 - [c20]Sebastià A. Bota, Jaume Verd
Cantilever NEMS relay-based SRAM devices for enhanced reliability. DTIS 2017: 1-6 - [c19]Bartomeu Alorda
6T CMOS SRAMs reliability monitoring through stability measurements. IOLTS 2017: 93-95 - 2016
- [j7]Bartomeu Alorda
An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies. Microelectron. Reliab. 65: 280-288 (2016) - [c18]Bartomeu Alorda
On-line write margin estimator to monitor performance degradation in SRAM cores. IOLTS 2016: 90-95 - 2014
- [j6]Bartomeu Alorda
Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54(11): 2613-2620 (2014) - [c17]Bartomeu Alorda, Cristian Carmona, Sebastià A. Bota:
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications. DATE 2014: 1-6 - [c16]Cristian Carmona
Energy consumption savings in ZigBee-based WSN adjusting power transmission at application layer. PATMOS 2014: 1-6 - 2013
- [c15]Sebastià A. Bota
Accurate alpha soft error rate evaluation in SRAM memories. IOLTS 2013: 205-209 - 2012
- [c14]Guillermo Rodríguez-Navas
Understanding the Role of Transmission Power in Component-Based Architectures for Adaptive WSN. COMPSAC Workshops 2012: 520-525 - [c13]Bartomeu Alorda
Multi-subject Project Based Learning initiative. EDUCON 2012: 1-7 - 2011
- [j5]Bartomeu Alorda
Design and evaluation of a microprocessor course combining three cooperative methods: SDLA, PjBL and CnBL. Comput. Educ. 57(3): 1876-1884 (2011) - [j4]Bartomeu Alorda
8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectron. Reliab. 51(2): 350-359 (2011) - [c12]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE 2011: 986-991 - 2010
- [j3]Gabriel Torrens
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 280-284 (2010) - [c11]Bartomeu Alorda, Gabriel Torrens
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE 2010: 429-434 - [c10]Sebastià A. Bota
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS 2010: 141-146
2000 – 2009
- 2009
- [c9]Sebastià A. Bota
Critical charge characterization in 6-T SRAMs during read mode. IOLTS 2009: 120-125 - 2007
- [j2]Bartomeu Alorda
Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. 1(5): 481-490 (2007) - 2005
- [c8]Bartomeu Alorda
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. IOLTS 2005: 177-182 - 2004
- [j1]Bartomeu Alorda, Vincent Canals
A Two-Level Power-Grid Model for Transient Current Testing Evaluation. J. Electron. Test. 20(5): 543-552 (2004) - [c7]Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura:
A BIST-based Charge Analysis for Embedded Memories. IOLTS 2004: 199-206 - 2003
- [c6]Bartomeu Alorda
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. IOLTS 2003: 178-182 - [c5]Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura:
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. ITC 2003: 719-726 - 2002
- [c4]Bartomeu Alorda
An Off-Chip Sensor Circuit for On-Line Transient Current Testing. IOLTW 2002: 192 - [c3]Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura:
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. ITC 2002: 947-953 - 2001
- [c2]Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden:
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS 2001: 286-291 - 2000
- [c1]Bartomeu Alorda
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW 2000: 87-91
Coauthor Index
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