default search action
Eric Martin 0001
Person information
- affiliation: Université de Bretagne-Sud
- award (2010): Knight of the Legion of Honour
Other persons with the same name
- Eric Martin — disambiguation page
- Eric Martin 0002
(aka: Eric Andre Martin) — University of New South Wales, Australia
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
- [j13]Loïck Simon
How Humans Comply With a (Potentially) Faulty Robot: Effects of Multidimensional Transparency. IEEE Trans. Hum. Mach. Syst. 53(4): 751-760 (2023) - 2021
- [c53]Nathalie Julien, Eric Martin:
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. SOHOMA 2021: 161-172
2010 – 2019
- 2012
- [c52]Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin:
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI 2012: 153-158 - 2011
- [c51]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP 2011: 1613-1616 - [c50]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS 2011: 1720-1723 - 2010
- [c49]Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin:
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL 2010: 464-468 - [c48]Cyrille Chavet
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP 2010: 1594-1597 - [c47]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS 2010: 466-469 - [c46]Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin:
Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS 2010: 531-534 - [i11]Cyrille Chavet
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. CoRR abs/1002.3990 (2010)
2000 – 2009
- 2009
- [j12]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. 56(2-3): 167-186 (2009) - 2008
- [j11]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques 27(1-2): 235-254 (2008) - 2007
- [j10]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
Constrained algorithmic IP design for system-on-chip. Integr. 40(2): 94-105 (2007) - [c45]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO 2007: 846-850 - [c44]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO 2007: 1625-1629 - [c43]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI 2007: 347-352 - [c42]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611 - [c41]Cyrille Chavet
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS 2007: 2946-2949 - [i10]Cyrille Chavet
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. CoRR abs/0706.1692 (2007) - [i9]Cyrille Chavet
A Design Methodology for Space-Time Adapter. CoRR abs/0706.2732 (2007) - [i8]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin:
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. CoRR abs/0706.2824 (2007) - [i7]Cyrille Chavet
Application of a design space exploration tool to enhance interleaver generation. CoRR abs/0706.3009 (2007) - [i6]Pierre Bomel, Eric Martin, Emmanuel Boutillon:
Synchronization Processor Synthesis for Latency Insensitive Systems. CoRR abs/0710.4659 (2007) - 2006
- [j9]Guillaume Savaton, Emmanuel Casseau, Eric Martin:
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. 86(7): 1375-1399 (2006) - [j8]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5(1): 29-53 (2006) - [j7]Fatma Sayadi, Emmanuel Casseau, Mohamed Atri
G729 Voice Decoder Design. J. VLSI Signal Process. 42(2): 173-184 (2006) - [c40]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS 2006: 244-249 - [i5]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power. CoRR abs/cs/0605142 (2006) - [i4]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006) - [i3]Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin:
A Memory Aware High Level Synthesis Too. CoRR abs/cs/0605144 (2006) - [i2]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware High-Level Synthesis for Embedded Systems. CoRR abs/cs/0605145 (2006) - [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin:
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006) - 2005
- [j6]Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. EURASIP J. Adv. Signal Process. 2005(16): 2641-2654 (2005) - [c39]Pierre Bomel, Eric Martin, Emmanuel Boutillon:
Synchronization Processor Synthesis for Latency Insensitive Systems. DATE 2005: 896-897 - [c38]Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
High-Level Synthesis in Latency Insensitive System Methodology. DSD 2005: 96-101 - [c37]Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin:
C-based rapid prototyping for digital signal processing. EUSIPCO 2005: 1-4 - [c36]Bertrand Le Gal, Emmanuel Casseau, Eric Martin:
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO 2005: 1-4 - [c35]Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart:
SystemCmantic: A high level Modelling and Co-Design Framework. FDL 2005: 341-353 - [c34]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin:
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) 2005: 61-64 - [c33]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683 - [c32]Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin:
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI 2005: 268-269 - [c31]Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz:
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. SAMOS 2005: 424-433 - 2004
- [j5]David Gnaedig, Emmanuel Boutillon, Eric Martin, Amor Nafkha, Michel Jézéquel, Jacky Tousch, Nathalie Brengarth:
Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur. Ann. des Télécommunications 59(3-4): 325-348 (2004) - [j4]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques 23(1): 35-66 (2004) - [c30]Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin:
Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47 - [c29]Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin:
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. DATE 2004: 666-667 - [c28]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95 - [c27]Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin:
A Complete Methodology for Memory Optimization in DSP Applications. DSD 2004: 98-103 - [c26]David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin:
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD 2004: 394-401 - [c25]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI 2004: 82-85 - [c24]Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin:
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) 2004: 45-48 - [c23]Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin:
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) 2004: 173-176 - [c22]Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280 - [c21]Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. PATMOS 2004: 342-351 - 2003
- [j3]Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin:
Power Consumption Modeling and Characterization of the TI C6201. IEEE Micro 23(5): 40-49 (2003) - [j2]Nathalie Julien, S. Gailhard, Eric Martin:
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. J. VLSI Signal Process. 35(2): 195-211 (2003) - [c20]Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin:
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. DATE 2003: 20250-20255 - [c19]Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin:
A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICASSP (2) 2003: 525-528 - [c18]Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin:
A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICME 2003: 817-820 - [c17]Philippe Coussy, Adel Baganne, Eric Martin:
Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC 2003: 38-43 - 2002
- [c16]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for integrating IP into SOC systems. CICC 2002: 307-310 - [c15]Philippe Coussy, Adel Baganne, Eric Martin:
IP cores integration in DSP System-on-chip designs. EUSIPCO 2002: 1-4 - [c14]Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin:
High-level design verification using Taylor Expansion Diagrams: first results. HLDVT 2002: 13-17 - [c13]Philippe Coussy, Adel Baganne, Eric Martin:
Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS 2002: 733-736 - [c12]Philippe Coussy, Adel Baganne, Eric Martin:
A design methodology for IP integration. ISCAS (4) 2002: 711-714 - [c11]Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin:
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. ISHPC 2002: 354-360 - [c10]Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin:
Power Consumption Estimation of a C Program for Data-Intensive Applications. PATMOS 2002: 332-341 - 2001
- [c9]Eric Senn, D. Emzivat, Eric Martin:
A smart "single line" pixel sensor for industrial vision. ICECS 2001: 405-408 - [c8]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS 2001: 535-538 - [c7]Eric Senn, Eric Martin:
A Vision System on Chip for Industrial Control. VLSI-SOC 2001: 27-38
1990 – 1999
- 1999
- [j1]Adel Baganne, Jean Luc Philippe, Eric Martin:
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller. J. VLSI Signal Process. 22(1): 21-29 (1999) - [c6]S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. Great Lakes Symposium on VLSI 1999: 334-335 - [c5]Christophe Jégo, Emmanuel Casseau, Eric Martin:
Architectural Synthesis with Interconnection Cost Control. VLSI 1999: 509-520 - 1998
- [c4]Stephane Gailhard, Nathalie Julien, Eric Martin:
Adaptive filters implementation performances under power dissipation constraint. EUSIPCO 1998: 1-4 - [c3]S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin:
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. Great Lakes Symposium on VLSI 1998: 426- - 1997
- [c2]Adel Baganne, Jean Luc Philippe, Eric Martin:
Hardware interface design for real time embedded systems. Great Lakes Symposium on VLSI 1997: 58-63 - 1993
- [c1]Eric Martin, Olivier Sentieys, Hélène Dubois, Jean Luc Philippe:
GAUT: An architectural synthesis tool for dedicated signal processors. EURO-DAC 1993: 14-19
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:59 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: