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Anees Ullah
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2020 – today
- 2024
- [j23]Shahid Ullah
, Yingmei Li
CO-19 PDB 2.0: A Comprehensive COVID-19 Database with Global Auto-Alerts, Statistical Analysis, and Cancer Correlations. Database J. Biol. Databases Curation 2024 (2024) - [c7]Achref Rebai
SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning. NAIC 2024: 61-68 - 2023
- [j22]Shahid Ullah
AVPCD: a plant-derived medicine database of antiviral phytochemicals for cancer, Covid-19, malaria and HIV. Database J. Biol. Databases Curation 2023 (2023) - [j21]Shanshan Liu
Error-Resilient Data Compression With Tunstall Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1963-1975 (2023) - [j20]Zhen Gao
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2003-2015 (2023) - [j19]Zhen Gao
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3770-3780 (2023) - [j18]Muhammad Awais
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs. ACM Trans. Embed. Comput. Syst. 22(4): 76:1-76:19 (2023) - [j17]Zhen Gao
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 142-146 (2023) - 2022
- [j16]Ali Zahir
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs. IEEE Embed. Syst. Lett. 14(1): 35-38 (2022) - [j15]Zhen Gao
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations. IEEE Trans. Emerg. Top. Comput. 10(2): 591-601 (2022) - [j14]Zhen Gao
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 291-302 (2022) - 2021
- [j13]Youcef Belkhier
Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System. IEEE Access 9: 57414-57425 (2021) - [j12]Anees Ullah
Switch-Based High Cardinality Node Detection. IEEE Embed. Syst. Lett. 13(4): 190-193 (2021) - [j11]Uzma M. Butt, Shoab A. Khan, Anees Ullah
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3351-3362 (2021) - [j10]Zhen Gao
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1073-1082 (2021) - 2020
- [j9]Ali Zahir
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2726-2730 (2020) - [c6]Anees Ullah, Salvatore Pontarelli, Pedro Reviriego:
FlexTCAM: Beyond Memory Based TCAM Emulation on FPGAs. NFV-SDN 2020: 110-113
2010 – 2019
- 2019
- [j8]Pedro Reviriego
Error Detection and Correction in SRAM Emulated TCAMs. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 486-490 (2019) - [j7]Pedro Reviriego
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1952-1956 (2019) - 2018
- [j6]Alexis Ramos
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Trans. Computers 67(2): 299-304 (2018) - [c5]Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir, Giuseppe Bianchi:
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays. HPSR 2018: 1-6 - 2017
- [j5]Nasim Ullah
Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems. IEEE Access 5: 7714-7723 (2017) - [j4]Luis Andrés Cardona, Anees Ullah
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. J. Syst. Archit. 81: 112-120 (2017) - [j3]Anees Ullah
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectron. Reliab. 75: 110-120 (2017) - [j2]Matteo Sonza Reorda
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers 66(6): 1022-1033 (2017) - 2015
- [b1]Anees Ullah:
Dependable System Design for Reconfigurable Safety-Critical Applications. Polytechnic University of Turin, Italy, 2015 - 2014
- [j1]Anees Ullah
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. J. Electron. Test. 30(4): 425-442 (2014) - [c4]Ernesto Sánchez, Luca Sterpone
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. FPL 2014: 1-6 - 2013
- [c3]Luca Sterpone
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs. AHS 2013: 9-14 - [c2]Luca Sterpone
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. AHS 2013: 184-188 - [c1]Matteo Sonza Reorda
An error-detection and self-repairing method for dynamically and partially reconfigurable systems. ETS 2013: 1-7 - 2012
- [i1]Sadaqat ur Rehman, Muhammad Bilal, Basharat Ahmad, Khawaja Muhammad Yahya, Anees Ullah, Obaid Ur Rehman:
Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN). CoRR abs/1203.3103 (2012)
Coauthor Index
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last updated on 2024-09-10 01:16 CEST by the dblp team
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