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Hsi-Che Tseng

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2010 – 2019

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2014
[c5]
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  dblp key:
  - conf/gcce/ChiLT14
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  - https://dblp.org/rec/conf/gcce/ChiLT14
Hsin-Chou Chi, Han-Sheng Liu, Hsi-Che Tseng:
A high-performance VLSI architecture for variable block size motion estimation. GCCE 2014: 123-124
2013
[c4]
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Hsin-Chou Chi, Hsi-Che Tseng, Chia-Wei Jeng:
Reconfigurable VLSI digital filters for tolerating multiple timing errors. GCCE 2013: 149-150
2011
[c3]
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  - conf/isocc/ChiTT11
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Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai:
Design of timing-error-resilient systolic arrays for matrix multiplication. ISOCC 2011: 219-222
[c2]
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  - conf/nesea/ChiTY11
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Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang:
Efficient diagnosable design of the IEEE P1500 architecture for SoC testing. NESEA 2011: 1-7

2000 – 2009

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2009
[c1]
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Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang:
Efficient diagnosis of scan chains with single stuck-at faults. CISS 2009: 473-476

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