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Jizeng Wei
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2020 – today
- 2022
- [c16]Bingchao Li, Jizeng Wei:
REMOC: efficient request managements for on-chip memories of GPUs. CF 2022: 1-11 - 2021
- [j14]Bingchao Li
, Jizeng Wei, Nam Sung Kim:
Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures. Microprocess. Microsystems 85: 104301 (2021) - 2020
- [j13]Zhen Xue
A Real-Time Naive Bayes Classifier Accelerator on FPGA. IEEE Access 8: 40755-40766 (2020)
2010 – 2019
- 2019
- [j12]Tengfei Wang, Wei Guo, Jizeng Wei:
Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves. Integr. 64: 13-21 (2019) - [j11]Bingchao Li, Jizeng Wei, Jizhou Sun, Murali Annavaram
An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns. ACM Trans. Archit. Code Optim. 16(3): 20:1-20:24 (2019) - [c15]Fanyu Shi, Jizeng Wei, Dazhi Sun, Guo Wei:
A Systematic Approach to Horizontal Clustering Analysis on Embedded RSA Implementation. ICPADS 2019: 901-906 - 2018
- [j10]Hui Wang, Wei Guo, Jizeng Wei:
Practical chosen-message CPA attack on message blinding exponentiation algorithm and its efficient countermeasure. World Wide Web 21(1): 201-217 (2018) - 2017
- [c14]Qingran Wang, Wei Guo, Dazhi Sun, Jizeng Wei:
A High Efficient Control Flow Authentication Method Basing on Loop Isolation. NCCET 2017: 96-103 - [c13]Wei Guo, Tenghai Wang, Jizeng Wei:
Malware Detection with Convolutional Neural Network Using Hardware Events. NCCET 2017: 104-115 - 2016
- [j9]Bingchao Li, Choungki Song, Jizeng Wei, Jung Ho Ahn
Exploring new features of high-bandwidth memory for GPUs. IEICE Electron. Express 13(14): 20160527 (2016) - [c12]Huicheng Peng, Jizeng Wei, Wei Guo:
Micro-architectural Features for Malware Detection. ACA 2016: 48-60 - [c11]Zhongyuan Hao, Wei Guo, Jizeng Wei, Dazhi Sun:
Dual Processing Engine Architecture to Speed Up Optimal Ate Pairing on FPGA Platform. Trustcom/BigDataSE/ISPA 2016: 584-589 - [c10]Kaiyuan Liang, Yanzhao Feng, Jizeng Wei, Wei Guo:
SecPage - A Lightweight Memory Protection Architecture. Trustcom/BigDataSE/ISPA 2016: 1917-1922 - 2015
- [j8]Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao:
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12(8): 20150111 (2015) - [j7]Jizeng Wei, Yisong Chang, Bingchao Li, Wei Guo, Jizhou Sun:
A modified post-TnL vertex cache for the multi-shader embedded GPUs. IEICE Electron. Express 12(10): 20150314 (2015) - [j6]Wei Guo, Kwanghyok Ri, Luping Cui, Jizeng Wei:
An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation. J. Circuits Syst. Comput. 24(10): 1550151:1-1550151:25 (2015) - [j5]Jingwei Hu, Wei Guo, Jizeng Wei, Ray C. C. Cheung
Fast and Generic Inversion Architectures Over GF(2m) Using Modified Itoh-Tsujii Algorithms. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 367-371 (2015) - [c9]Kothiya Mayank, Hongwen Dai, Jizeng Wei, Huiyang Zhou
Analyzing graphics processor unit (GPU) instruction set architectures. ISPASS 2015: 155-156 - 2014
- [j4]Jizeng Wei, Xulong Liu, Hao Liu, Wei Guo:
A low-time-complexity and secure dual-field scalar multiplication based on co-Z protected NAF. IEICE Electron. Express 11(11): 20140361 (2014) - [c8]Zhaojing Ding, Wei Guo, Liangjian Su, Jizeng Wei, Haihua Gu:
Further Research on N-1 Attack against Exponentiation Algorithms. ACISP 2014: 162-175 - [c7]Ya Tan, Jizeng Wei, Wei Guo:
The Micro-architectural Support Countermeasures against the Branch Prediction Analysis Attack. TrustCom 2014: 276-283 - 2013
- [j3]Jingwei Hu, Wei Guo, Jizeng Wei, Ray C. C. Cheung
A scalable RNS Montgomery multiplier over F2m. IEICE Electron. Express 10(23): 20130704 (2013) - [j2]Wei Guo, Jingwei Hu, Jizeng Wei:
A TTA-like Processor for Fast RSA Key Generation Using RNS. J. Comput. 8(1): 33-40 (2013) - [j1]Yisong Chang, Jizeng Wei, Wei Guo, Jizhou Sun:
A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications. Microprocess. Microsystems 37(6-7): 725-738 (2013) - [c6]Jizeng Wei, Wei Guo, Hao Liu, Ya Tan:
A Unified Cryptographic Processor for RSA and ECC in RNS. NCCET 2013: 19-32 - 2011
- [c5]Jingwei Hu, Wei Guo, Jizeng Wei, Yisong Chang, Dazhi Sun:
A Novel Architecture for Fast RSA Key Generation Based on RNS. PAAP 2011: 345-349 - [c4]Hao Liu, Wei Guo, Chao Lu, Jizeng Wei:
An Efficient Stereoscopic Game Conversion System for Embedded Platform. TrustCom 2011: 1235-1240 - [c3]Jizeng Wei, Yisong Chang, Wei Guo, Jizhou Sun:
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit. VLSI-SoC 2011: 188-191
2000 – 2009
- 2009
- [c2]Wei Guo, Jizeng Wei, Yongbin Yao, Zaifeng Shi, Su Wang:
Design of a Configurable and Extensible Tcore Processor Based on Transport Triggered Architecture. CSIE (3) 2009: 536-540 - 2008
- [c1]Jizeng Wei, Wei Guo, Jizhou Sun, Zaifeng Shi:
Design and implementation of co-design toolset for tcore processor. APCCAS 2008: 1664-1667
Coauthor Index
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