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Steffen Kunze
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2010 – 2019
- 2014
- [c6]Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny:
10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. ISSCC 2014: 188-189 - 2013
- [b1]Steffen Kunze:
On the design and implementation of multi-mode channel decoders. Dresden University of Technology, Vogt 2013, ISBN 978-3-938860-66-3, pp. 1-88 - 2012
- [c5]Markus Winter, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori:
A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. ISSCC 2012: 216-218 - 2011
- [c4]Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Tomoyoshi Kobori:
Combining LDPC, turbo and Viterbi decoders: Benefits and costs. SiPS 2011: 216-221
2000 – 2009
- 2009
- [c3]Steffen Kunze, Emil Matús, Gerhard P. Fettweis:
ASIP Decoder Architecture for Convolutional and LDPC Codes. ISCAS 2009: 2457-2460 - 2008
- [c2]Marcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard P. Fettweis:
Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. ASAP 2008: 215-220 - [c1]Marcos B. S. Tavares, Emil Matús, Steffen Kunze, Gerhard P. Fettweis:
A dual-core programmable decoder for LDPC convolutional codes. ISCAS 2008: 532-535
Coauthor Index
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