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Mrinal Bose
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2000 – 2009
- 2009
- [c9]Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra:
Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344 - [c8]Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller:
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED 2009: 377-381 - [c7]Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra:
Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. ISVLSI 2009: 241-246 - [c6]Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen
, Mrinal Bose, Jayanta Bhadra:
Portable simulation/emulation stimulus on an industrial-strength SoC. ITC 2009: 1 - [c5]Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra:
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. MTV 2009: 3-8 - 2003
- [c4]Mrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes:
Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification. MTV 2003: 7-10 - 2001
- [c3]Mrinal Bose, Jongshin Shin, Elizabeth M. Rudnick, Todd Dukes, Magdy Abadir:
A genetic approach to automatic bias generation for biased random instruction generation. CEC 2001: 442-448 - [c2]Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir:
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65-
1990 – 1999
- 1999
- [c1]Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose:
Controlling State Explosion in Static Simulation by Selective Composition. VLSI Design 1999: 226-231
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