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Gerald G. Pechanek
Person information
- affiliation: BOPS
- affiliation: IBM
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2010 – 2019
- 2017
- [c13]Gerald G. Pechanek, Nikos Pitsianis:
An introduction to an array memory processor for application specific acceleration. HPEC 2017: 1-7
2000 – 2009
- 2003
- [j7]Nikos Pitsianis, Gerald G. Pechanek:
Indirect VLIW memory allocation for the ManArray multiprocessor DSP. SIGARCH Comput. Archit. News 31(1): 69-74 (2003) - 2001
- [j6]Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, D. G. Pechanek:
On Chaos and Neural Networks: The Backpropagation Paradigm. Artif. Intell. Rev. 15(3): 165-187 (2001) - 2000
- [j5]Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, Gerald G. Pechanek:
A look inside the learning process of neural networks. Complex. 5(6): 34-38 (2000) - [c12]Gerald G. Pechanek, Stamatis Vassiliadis:
The ManArray( Embedded Processor Architecture. EUROMICRO 2000: 1348-1355 - [c11]Bruce Schulman, Gerald G. Pechanek:
A 90k Gate "CLB" for Parallel Distributed Computing. IPDPS Workshops 2000: 831-838
1990 – 1999
- 1999
- [j4]Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis:
A neuro-emulator with embedded capabilities for generalized learning. J. Syst. Archit. 45(14): 1219-1243 (1999) - [c10]Gerald G. Pechanek, Stamatis Vassiliadis, Nikos Pitsianis
:
ManArray Processor Interconnection Network: An Introduction. Euro-Par 1999: 761-765 - 1998
- [j3]Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, D. G. Pechanek:
Chaos and Neural Network Learning. Some Observations. Neural Process. Lett. 7(2): 69-80 (1998) - [c9]Stamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek:
The Sum-Absolute-Difference Motion Estimation Accelerato. EUROMICRO 1998: 20559-20566 - 1996
- [c8]Chris H. L. Moller, Gerald G. Pechanek:
Architectural simulation system for M.f.a.s.t. Annual Simulation Symposium 1996: 221- - [c7]Valentine C. Aikens II, José G. Delgado-Frias, Steven M. Barber, Gerald G. Pechanek, Stamatis Vassiliadis:
A neuro-emulator with learning and virtual emulation capabilities. ICNN 1996: 1355-1360 - 1995
- [c6]Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, D. G. Pechanek:
XOR and backpropagation learning: in and out of the chaos? ESANN 1995 - [c5]Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner:
MFAST: a single chip highly parallel image processing architecture. ICIP 1995: 69-72 - [c4]Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis:
A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106 - 1993
- [j2]Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias:
Spin: the Sequential Pipelined Neuroemulator. Int. J. Artif. Intell. Tools 2(1): 117-132 (1993) - [c3]Gerald G. Pechanek, José G. Delgado-Frias
A massively parallel diagonal-fold array processor. ASAP 1993: 140-143 - 1992
- [j1]Gerald G. Pechanek, Stamatis Vassiliadis, José G. Delgado-Frias
Digital neural emulators using tree accumulation and communication structures. IEEE Trans. Neural Networks 3(6): 934-950 (1992) - 1991
- [c2]Nikolaos G. Bourbakis, Robin Williams, Forouzan Golshani, Myron Flickner, Ted Laliotis, Sukhan Lee, José G. Delgado-Frias, Dan Hammerstrom, Cris Koutsougeras, Gerald G. Pechanek, Benjamin W. Wah, John Yen, Farokh B. Bastani, Tom Cooper, Karan Harbison-Briggs, Rudy Lauber, Alun D. Preece, Imran A. Zualkernan, W. T. Tsai, Daniel E. Cooke, Martin S. Feather, Stephen Fickas, N. Minsky, Peter G. Selfridge, Douglas Smith:
AI in multimedia (panel session). ICTAI 1991: 3-12 - [c1]Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias
SPIN: a sequential pipelined neurocomputer. ICTAI 1991: 74-81
Coauthor Index
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