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Ji-Jan Chen
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2010 – 2019
- 2015
- [j4]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo
, Liyang Lai, Ting-Pu Tai, Xiaowei Li
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 466-479 (2015) - 2013
- [c13]Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim:
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC 2013: 1-10 - [c12]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC 2013: 1-10 - 2012
- [c11]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10 - 2011
- [c10]Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen:
Black-box leakage power modeling for cell library and SRAM compiler. DATE 2011: 637-642 - [c9]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - 2010
- [j3]Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu
Diagnosis of MRAM Write Disturbance Fault. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1762-1766 (2010) - [c8]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c7]Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen:
An embedded wide-range and high-resolution CLOCK jitter measurement circuit. DATE 2010: 1637-1640
2000 – 2009
- 2008
- [j2]Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2097-2101 (2008) - [c6]Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock. ATS 2008: 268 - 2007
- [j1]Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 767-776 (2007) - [c5]Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen:
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement. ATS 2007: 219-223 - [c4]Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu
Diagnosis for MRAM write disturbance fault. ITC 2007: 1-9 - 2006
- [c3]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8 - 2005
- [c2]Charles H.-P. Wen
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. ITC 2005: 10 - [c1]Charles H.-P. Wen, Li-C. Wang
On A Software-Based Self-Test Methodology and Its Application. VTS 2005: 107-113
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