default search action
Jongsun Park 0001
Jong Sun Park 0001
Person information
- affiliation: Korea University, School of Electrical Engineering, Seoul, South Korea
- affiliation (PhD 2005): Purdue University, West Lafayette, IN, USA
Other persons with the same name
- Jongsun Park — disambiguation page
- Jongsun Park 0002
— InfoBoss Co. Ltd., Seoul, South Korea (and 1 more)
- Jong Sun Park 0003 — BaekSeok University, Department of Law, Cheonan-si, South Korea
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j74]Kyeongho Lee
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits 59(6): 1926-1937 (2024) - [j73]Dongsu Kim, Taehwan Kim, Yunho Jang
SOT-MRAM-Based LUT Cell Design for Area- and Energy-Efficient FPGA. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4276-4280 (2024) - [c75]Han Cho, Dongjun Kim, Seungeon Hwang, Jongsun Park:
SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering. DAC 2024: 181:1-181:6 - [c74]Yunho Jang
STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency. ISLPED 2024: 1-6 - [c73]Dongjun Kim
iSPADE: End-to-end Sparse Architecture for Dense DNN Acceleration via Inverted-bit Representation. ISLPED 2024: 1-6 - 2023
- [j72]Joongho Jo, Geonho Kim, Seungtae Kim, Jongsun Park
LoCoExNet: Low-Cost Early Exit Network for Energy Efficient CNN Accelerator Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4909-4921 (2023) - [j71]Sungsoo Cheon
A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2085-2097 (2023) - [j70]Junhyun Song, Kyeongho Lee
Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1169-1173 (2023) - [j69]Dongyeob Shin, Geonho Kim
Low Complexity Gradient Computation Techniques to Accelerate Deep Neural Network Training. IEEE Trans. Neural Networks Learn. Syst. 34(9): 5745-5759 (2023) - 2022
- [j68]Sunghyun Choi
Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design. IEEE Trans. Biomed. Circuits Syst. 16(3): 442-455 (2022) - [j67]Yunho Jang
Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning. IEEE Trans. Computers 71(9): 2022-2035 (2022) - [j66]Taehwan Kim, Yunho Jang
SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication. IEEE Trans. Computers 71(11): 2816-2828 (2022) - [j65]Jooyoon Kim
A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 2049-2059 (2022) - [j64]Yunho Jang
Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1622-1626 (2022) - [c72]Dongsu Kim, Yunho Jang, Taehwan Kim, Jongsun Park:
BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing. AICAS 2022: 74-77 - [c71]Hyunchul Park, Kyeongho Lee, Jongsun Park:
A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. AICAS 2022: 455-458 - [c70]Dongwoo Lew
A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design. DAC 2022: 265-270 - [c69]Kyeongho Lee, Joonhyung Kim, Jongsun Park:
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. ICCAD 2022: 143:1-143:8 - [c68]Joonhyung Kim, Kyeongho Lee, Jongsun Park:
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. ISLPED 2022: 6:1-6:6 - [c67]Taehwan Kim, Jongsun Park:
Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation. ISOCC 2022: 3-4 - [c66]Hyeyeong Lee, Joonhyung Kim, Jongsun Park:
SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. ISOCC 2022: 5-6 - [c65]Hyunchul Park, Jongsun Park:
Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. ISOCC 2022: 7-8 - [c64]Yeseul Kim, Jongsun Park:
Energy-Efficient STT-MRAM based Digital PIM supporting Vertical Computations Using Sense Amplifier. ISOCC 2022: 9-10 - [c63]Dongsu Kim, Jongsun Park:
Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM Architecture. ISOCC 2022: 29-30 - [c62]Minseo Kim, Jongsun Park:
High Detection Rate BCH Code with CRC Code for Memory Application. ISOCC 2022: 35-36 - [c61]Han Cho, Jongsun Park:
Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory Accesses. ISOCC 2022: 71-72 - [c60]Seungeon Hwang, Jongsun Park:
Percentile Clipping based Low Bit-Precision Quantization for Depth Estimation Network. ISOCC 2022: 73-74 - [c59]Dongwoo Lew, Jongsun Park:
A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning Hardware. ISOCC 2022: 97-98 - [c58]Seongyoon Kang, Jongsun Park:
Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. ISOCC 2022: 103-104 - [c57]Joonhyung Kim, Jongsun Park:
The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network Applications. ISOCC 2022: 129-130 - [c56]Kyungchul Lee, Jongsun Park:
Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification Networks. ISOCC 2022: 370-371 - [c55]Joongho Jo, Jongsun Park:
Class Difficulty based Mixed Precision Quantization for Low Complexity CNN Training. ISOCC 2022: 372-373 - [i3]Dongwoo Lew, Kyungchul Lee, Jongsun Park:
A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design. CoRR abs/2208.04494 (2022) - [i2]Joonhyung Kim, Kyeongho Lee, Jongsun Park:
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. CoRR abs/2211.16008 (2022) - 2021
- [j63]Jinho Jeong
An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design. IEEE Commun. Lett. 25(5): 1505-1509 (2021) - [j62]Kyeongho Lee, Woong Choi
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. IEEE J. Solid State Circuits 56(8): 2574-2584 (2021) - [j61]Nahsung Kim, Dongyeob Shin, Wonseok Choi, Geonho Kim
Exploiting Retraining-Based Mixed-Precision Quantization for Low-Cost DNN Accelerator Design. IEEE Trans. Neural Networks Learn. Syst. 32(7): 2925-2938 (2021) - [j60]Daehan Ji
An Error Compensation Technique for Low-Voltage DNN Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 397-408 (2021) - [c54]Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park:
A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. DAC 2021: 739-744 - [c53]Jooyoon Kim, Kwanho Bae, Jongsun Park:
Low Power SOT-MRAM Cell Configuration For Dual Write Operation. ICEIC 2021: 1-3 - [c52]Junhyun Song, Junghoon Cho, Jongsun Park:
Key Length Reconfigurable ARIA Hardware with S-box Optimization. ICEIC 2021: 1-3 - [c51]Seunghwan Bang, Dongwoo Lew
An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction. IJCNN 2021: 1-8 - [c50]Junghoon Cho, Junhyun Song, Jongsun Park:
Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance. ISCAS 2021: 1-5 - [c49]Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park:
Low Energy Domain Wall Memory Based Convolution Neural Network Design with Optimizing MAC Architecture. ISCAS 2021: 1-4 - [c48]Dongsu Kim, Jongsun Park:
Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. ISOCC 2021: 77-78 - [c47]Joonhyung Kim, Jongsun Park:
A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. ISOCC 2021: 89-90 - [c46]Hyunchul Park, Jongsun Park:
Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. ISOCC 2021: 105-106 - 2020
- [j59]Jinil Chung
Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers. IEEE Access 8: 19783-19798 (2020) - [j58]Hoyoung Tang, Donghyeon Cho, Dongwoo Lew
Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates. Neurocomputing 407: 300-312 (2020) - [j57]Heetak Kim, Hoyoung Tang
An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability. IEEE Trans. Biomed. Circuits Syst. 14(1): 125-137 (2020) - [c45]Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. DAC 2020: 1-6 - [c44]Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park:
Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training. DAC 2020: 1-6 - [c43]Taehwan Kim, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, Jongsun Park:
Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM. ISCAS 2020: 1-5 - [c42]Kwanho Bae, Jongsun Park:
Efficient TSV Fault Detection Scheme For High Bandwidth Memory Using Pattern Analysis. ISOCC 2020: 19-20 - [c41]Sunghyun Choi, Jongsun Park:
Early Termination of STDP Learning with Spike Counts in Spiking Neural Networks. ISOCC 2020: 75-76 - [c40]Dongwoo Lew, Jongsun Park:
Early Image Termination Technique During STDP Training of Spiking Neural Network. ISOCC 2020: 79-80 - [c39]Geonho Kim, Jongsun Park:
Low Cost Early Exit Decision Unit Design for CNN Accelerator. ISOCC 2020: 127-128 - [c38]Joongho Jo, Jongsun Park:
Confidence Score based Mini-batch Skipping for CNN Training on Mini-batch Training Environment. ISOCC 2020: 129-130 - [c37]Jooyoon Kim, Jongsun Park:
Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit. ISOCC 2020: 147-148 - [c36]Jinho Jeong, Jongsun Park:
Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter. ISOCC 2020: 292-293 - [c35]Sungsoo Cheon, Jongsun Park:
A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. ISOCC 2020: 294-295 - [c34]Junghoon Cho, Junhyun Song, Jongsun Park:
Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification. ISOCC 2020: 304-305 - [i1]Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. CoRR abs/2008.03378 (2020)
2010 – 2019
- 2019
- [j56]Won Jun Lee
Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors. IEEE Access 7: 82633-82648 (2019) - [j55]Dongyeob Shin, Wonseok Choi, Jongsun Park
Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 520-531 (2019) - [j54]Seyedhamidreza Motaman
A Perspective on Test Methodologies for Supervised Machine Learning Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 562-569 (2019) - [j53]Bohun Kim
Compact Implementations of HIGHT Block Cipher on IoT Platforms. Secur. Commun. Networks 2019: 5323578:1-5323578:10 (2019) - [j52]Hoyoung Tang
Spike Counts Based Low Complexity SNN Architecture With Binary Synapse. IEEE Trans. Biomed. Circuits Syst. 13(6): 1664-1677 (2019) - [j51]Gyuseong Kang, Jongsun Park
Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1343-1352 (2019) - [c33]Wonseok Choi, Dongyeob Shin, Jongsun Park
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators. DAC 2019: 204 - [c32]Kyeongho Lee, Geon Ko, Jongsun Park
Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. ISCAS 2019: 1-4 - [c31]Heetak Kim, Hoyoung Tang, Jongsun Park
An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. ISLPED 2019: 1-6 - 2018
- [j50]Byeonggil Park, Jongsun Park
Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions. IEEE Access 6: 14498-14509 (2018) - [j49]Woong Choi, Kyungrak Choi
Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction. IEEE Access 6: 14734-14746 (2018) - [j48]Cheolhwan Kim, Dongyeob Shin, Bohun Kim, Jongsun Park
Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 770-781 (2018) - [j47]Dongyeob Shin, Jongsun Park
A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2606-2616 (2018) - [j46]Juseong Lee, Hoyoung Tang, Jongsun Park
Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications. IEEE Trans. Circuits Syst. Video Technol. 28(4): 1037-1046 (2018) - [c30]Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
Content addressable memory based binarized neural network accelerator using time-domain signal processing. DAC 2018: 138:1-138:6 - [c29]Hoyoung Tang, Heetak Kim, Donghyeon Cho, Jongsun Park
Spike Counts Based Low Complexity Learning with Binary Synapse. IJCNN 2018: 1-8 - [c28]Woong Choi, Kyeongho Lee, Jongsun Park
Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. ISCAS 2018: 1-4 - [c27]Gyuseong Kang, Yunho Jang, Jongsun Park
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM. ISCAS 2018: 1-4 - [c26]Gyuseong Kang, Yunho Jang, Jongsun Park
Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning. ISLPED 2018: 21:1-21:6 - [c25]Taehwan Kim, Jongsun Park
Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. ISOCC 2018: 19-20 - [c24]Byungjun Choi, Bohun Kim, Jongsun Park
Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique. ISOCC 2018: 46-47 - [c23]Woong Choi, Jongsun Park
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. VLSI Circuits 2018: 17-18 - 2017
- [j45]Dongyeob Shin, Jongsun Park
Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test 34(6): 84-93 (2017) - [j44]Asmit De
Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions. J. Hardw. Syst. Secur. 1(4): 328-339 (2017) - [j43]Woong Choi, Jongsun Park
Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1511-1521 (2017) - [j42]Byeonggil Park, Seungyong An, Jongsun Park
Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 535-539 (2017) - [j41]Kyungho Shin, Woong Choi, Jongsun Park
Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2036-2048 (2017) - [j40]Gyuseong Kang, Woong Choi, Jongsun Park
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3484-3494 (2017) - [c22]Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park
A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication. CICC 2017: 1-4 - [c21]Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park
Bit-width reduction and customized register for low cost convolutional neural network accelerator. ISLPED 2017: 1-6 - [c20]Wonseok Choi, Jongsun Park
An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. ISOCC 2017: 103-104 - 2016
- [j39]Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 265-278 (2016) - [j38]Jinil Chung, Kenneth Ramclam, Jongsun Park
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 91-102 (2016) - [j37]Woong Choi, Jongsun Park
A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1164-1175 (2016) - [j36]Sandip Ray, Jongsun Park
Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape. IEEE Trans. Multi Scale Comput. Syst. 2(2): 123-128 (2016) - [j35]Chan-Keun Kwon, Hoon Ki Kim, Jongsun Park
A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1184-1188 (2016) - [j34]Hoyoung Tang, Jongsun Park
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2397-2401 (2016) - [c19]Gihoon Jung, Kyungrak Choi, Jongsun Park
A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. APCCAS 2016: 180-183 - [c18]Jinil Chung, Jongsun Park
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. ISLPED 2016: 332-337 - [c17]Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park
Customized SRAM design for low power video code applications. ISOCC 2016: 79-80 - 2015
- [j33]Woong Choi, Gyuseong Kang, Jongsun Park
A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. IEEE J. Solid State Circuits 50(10): 2451-2462 (2015) - [j32]Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park
D2ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing. Microprocess. Microsystems 39(8): 767-781 (2015) - [j31]Sandip Ray, Jongsun Park
Guest Editors' Introduction: Wearables, Implants, and Internet of Things. IEEE Trans. Multi Scale Comput. Syst. 1(2): 60-61 (2015) - [c16]Jinil Chung, Kenneth Ramclam, Jongsun Park
Domain wall memory based digital signal processors for area and energy-efficiency. DAC 2015: 64:1-64:6 - [c15]Jae-Won Jang, Jongsun Park
Self-correcting STTRAM under magnetic field attacks. DAC 2015: 77:1-77:6 - [c14]Hoyoung Tang, Gihoon Jung, Jongsun Park
A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. ISCAS 2015: 1997-2000 - 2014
- [j30]Ji-Hwan Yoon, Jongsun Park
An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder. Circuits Syst. Signal Process. 33(11): 3457-3473 (2014) - [j29]Jangwon Park, Jongsun Park
VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs 61-II(2): 120-124 (2014) - [j28]Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1060-1068 (2014) - [j27]Anandaroop Ghosh, Somnath Paul, Jongsun Park
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1314-1327 (2014) - [c13]Ji-Hwan Yoon, Dongyeob Shin, Jongsun Park
A low-complexity composite QR decomposition architecture for MIMO detector. ISCAS 2014: 1692-1695 - 2013
- [j26]Young-Jae Min, Hoon Ki Kim, Yu-Ri Kang, Gil-Su Kim, Jongsun Park
Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers. IEEE Trans. Biomed. Circuits Syst. 7(4): 426-436 (2013) - [j25]Phi-Hung Pham, Junyoung Song, Jongsun Park
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 173-177 (2013) - [j24]Insoo Lee, Jinmo Kwon, Jangwon Park, Jongsun Park
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System. J. Signal Process. Syst. 73(2): 123-136 (2013) - [c12]Iput Heri Kurniawan, Ji-Hwan Yoon, Jongsun Park
Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers. ISCAS 2013: 2159-2162 - [c11]Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park
Reconfigurable ECC for adaptive protection of memory. MWSCAS 2013: 1085-1088 - 2012
- [j23]Woojin Rim, Woong Choi, Jongsun Park
Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 587-591 (2012) - [j22]Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park, Jongsun Park
Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2275-2284 (2012) - [j21]Phi-Hung Pham, Jongsun Park
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 270-283 (2012) - [j20]Seokjoong Hwang, Youngsun Han
Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1248-1261 (2012) - [c10]Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
High-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver. ISCAS 2012: 21-24 - [c9]Dongwan Kim, Wan-Seon Lim, Jongsun Park
Dual queue based rate selecting schedule for throughput enhancement in WLANs. ISCAS 2012: 540-543 - 2011
- [j19]Kyu-Young Kim, Young-Jae Min, Soo-Won Kim, Jongsun Park
Low-power programmable divider with a shared counter for frequency synthesiser. IET Circuits Devices Syst. 5(3): 170-176 (2011) - [j18]Kyu-Young Kim, Yonghwan Kim, Doo-Chan Lee, Yu-Ri Kang, Hoon Ki Kim, Soo-Won Kim, Jongsun Park
An Energy Efficient VPP Generator With Fast Ramp-Up Time for Mobile DRAM. IEEE J. Solid State Circuits 46(6): 1488-1494 (2011) - [j17]Doo-Chan Lee, Kyu-Young Kim, Young-Jae Min, Jongsun Park
A Jitter and Power Analysis on DCO. IEEE Trans. Circuits Syst. II Express Briefs 58-II(9): 560-564 (2011) - [j16]Seok-Jae Lee, Ji-Woong Choi, Seon Wook Kim, Jongsun Park
A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2221-2228 (2011) - [c8]Ji-Woong Choi, Jungwon Lee, Hui-Ling Lou, Jongsun Park
Improved MIMO SIC Detection Exploiting ML Criterion. VTC Fall 2011: 1-5 - 2010
- [j15]Phi-Hung Pham, Jongsun Park
ProMINoC: An efficient Network-on-Chip design for flexible data permutation. IEICE Electron. Express 7(12): 861-866 (2010) - [j14]Ik Joon Chang, Jongsun Park
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. IET Circuits Devices Syst. 4(6): 469-478 (2010) - [j13]Hee-Dong Kim, Ho-Myoung An, Yujeong Seo, Yongjie Zhang, Jongsun Park
Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories. Microelectron. Reliab. 50(1): 21-25 (2010) - [j12]Ji-Woong Choi, Jungwon Lee, Byung Gueon Min, Jongsun Park
Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 632-636 (2010) - [j11]Jongsun Park
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 787-793 (2010) - [j10]Yongtao Wang, Hamid Mahmoodi
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. 58(2): 125-137 (2010)
2000 – 2009
- 2009
- [j9]Jungwon Lee, Ji-Woong Choi, Hui-Ling Lou, Jongsun Park
Soft MIMO ML demodulation based on bitwise constellation partitioning. IEEE Commun. Lett. 13(10): 736-738 (2009) - [j8]Sung-Hak Song, Chang-Hoon Lee, Ju-Hyun Park, Kyo-Jun Koo, Jong-Kook Kim
Enhancing Location Estimation and Reducing Computation using Adaptive Zone Based K-NNSS Algorithm. KSII Trans. Internet Inf. Syst. 3(1): 119-133 (2009) - [j7]Seokhwan Kim, Kyeong Hur, Jongsun Park
A fair distributed resource allocation method in UWB wireless PANs with WiMedia MAC. J. Commun. Networks 11(4): 375-383 (2009) - [j6]Jin-Woo Kim, Kyeong Hur, Jongsun Park
A distributed MAC design for data collision-free wireless USB home networks. IEEE Trans. Consumer Electron. 55(3): 1337-1343 (2009) - [j5]Seung Beom Lee, Kyeong Hur, Jongsun Park
A packet forwarding controller for mobile IP-based networks with packet buffering. IEEE Trans. Consumer Electron. 55(3): 1344-1350 (2009) - 2008
- [j4]Jongsun Park
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. J. Signal Process. Syst. 53(3): 399-410 (2008) - 2006
- [j3]Jongsun Park
Efficient modeling of 1/falpha/ noise using multirate process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1247-1256 (2006) - [c7]Jongsun Park, Jung Hwan Choi, Kaushik Roy:
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE 2006: 520-521 - 2004
- [j2]Jongsun Park
Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits 39(2): 348-357 (2004) - [c6]Jongsun Park, Kaushik Roy:
A low power reconfigurable DCT architecture to trade off image quality for computational complexity. ICASSP (5) 2004: 17-20 - [c5]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) 2004: 97-100 - 2003
- [j1]Jongsun Park
High-performance FIR filter design based on sharing multiplication. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 244-253 (2003) - [c4]Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient generation of 1/fα noise using a multi-rate filter bank. CICC 2003: 707-710 - 2002
- [c3]Jongsun Park, Soonkeon Kwon, Kaushik Roy:
Low power reconfigurable DCT design based on sharing multiplication. ICASSP 2002: 3116-3119 - [c2]Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy:
High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300 - 2000
- [c1]Jongsun Park
Non-adaptive and adaptive filter implementation based on sharing multiplication. ICASSP 2000: 460-463
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-13 23:45 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: