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Joaquín Cerdá
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2020 – today
- 2021
- [j5]Joaquín Cerdá, Javier Sánchez-Sánchez
, David Viejo-Romero
Characterisation of Goal Scoring Patterns during Open Play Related to Zone Pitch Division and Number of Players Involved in the 2018 FIFA World Cup. Sensors 21(16): 5601 (2021)
2010 – 2019
- 2014
- [j4]C. Montoliu, Néstor Ferrando
Application of the level set method for the visual representation of continuous cellular automata oriented to anisotropic wet etching. Int. J. Comput. Math. 91(1): 124-134 (2014) - 2013
- [j3]C. Montoliu, Néstor Ferrando
Implementation and evaluation of the Level Set method: Towards efficient and accurate simulation of wet etching for microengineering applications. Comput. Phys. Commun. 184(10): 2299-2309 (2013) - [j2]Joaquín Cerdá
LGEM: A lattice Boltzmann economic model for income distribution and tax regulation. Math. Comput. Model. 57(7-8): 1648-1655 (2013) - 2011
- [j1]Néstor Ferrando
Octree-based, GPU implementation of a continuous cellular automaton for the simulation of complex, evolving surfaces. Comput. Phys. Commun. 182(3): 628-640 (2011) - 2010
- [c8]Manuel Rivas Pérez
Visual spike-based convolution processing with a Cellular Automata architecture. IJCNN 2010: 1-7
2000 – 2009
- 2009
- [c7]Ramón José Aliaga
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. ICSAMOS 2009: 1-8 - 2008
- [c6]Alejandro Linares-Barranco
AER filtering using GLIDER: VHDL cellular automata description. ICECS 2008: 614-617 - 2005
- [c5]Joaquín Cerdá
A Tool for Implementing and Exploring SBM Models: Universal 1D Invertible Cellular Automata. IWINAC (1) 2005: 279-289 - 2003
- [c4]Joaquín Cerdá
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. FPL 2003: 776-785 - [c3]Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo
A new inverse discrete wavelet packet transform architecture. ISSPA (2) 2003: 443-446 - [c2]Joaquín Cerdá
Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) 2003: 121-128 - 2000
- [c1]Rafael Gadea Gironés
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS 2000: 225-230
Coauthor Index
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