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Peng Huang 0004
Person information
- affiliation: Peking University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Peng Huang — disambiguation page
- Peng Huang 0001 — University of Surrey, UK
- Peng Huang 0002
— Tongji University, State Key Laboratory of Disaster Reduction in Civil Engineering, Shanghai, China
- Peng Huang 0003
- Peng Huang 0005
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2020 – today
- 2024
- [j11]Lixia Han
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2043-2056 (2024) - [c18]Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu, Jinfeng Kang:
Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators. DATE 2024: 1-2 - [c17]Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Lifeng Liu, Linxiao Shen, Peng Huang, Xiaoyan Liu, Jinfeng Kang:
Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network. ISCAS 2024: 1-5 - 2023
- [j10]Guihai Yu, Peng Huang, Runze Han, Lixia Han, Xiaoyan Liu, Jinfeng Kang:
Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy. Sci. China Inf. Sci. 66(2) (2023) - [j9]Haozhang Yang, Peng Huang, Runze Han, Xiaoyan Liu, Jinfeng Kang:
An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash. Sci. China Inf. Sci. 66(4) (2023) - [j8]Shiyue Song, Peng Huang, Wensheng Shen, Lifeng Liu, Jinfeng Kang:
A 3.3-Mbit/s true random number generator based on resistive random access memory. Sci. China Inf. Sci. 66(11) (2023) - [c16]Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Xiaoyan Liu, Jinfeng Kang:
A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization. DAC 2023: 1-6 - 2022
- [j7]Runze Han
Floating Gate Transistor-Based Accurate Digital In-Memory Computing for Deep Neural Networks. Adv. Intell. Syst. 4(12) (2022) - [j6]Lixia Han
Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4487-4498 (2022) - 2021
- [j5]Runze Han, Yachen Xiang, Peng Huang, Yihao Shan, Xiaoyan Liu, Jinfeng Kang
Flash Memory Array for Efficient Implementation of Deep Neural Networks. Adv. Intell. Syst. 3(5): 2000161 (2021) - [c15]Lixia Han, Yachen Xiang, Peng Huang, Guihai Yu, Runze Han, Xiaoyan Liu, Jinfeng Kang:
Novel Weight Mapping Method for Reliable NVM based Neural Network. IRPS 2021: 1-6
2010 – 2019
- 2019
- [j4]Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang:
Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. Sci. China Inf. Sci. 62(2): 22401:1-22401:11 (2019) - [j3]Yuning Jiang, Peng Huang, Zheng Zhou, Jinfeng Kang:
Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning. Sci. China Inf. Sci. 62(6): 62408:1-62408:19 (2019) - [j2]Runze Han
A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1692-1703 (2019) - [c14]Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang:
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. ASAP 2019: 157-164 - [c13]Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu:
Flash-based Computing in-Memory Scheme for IOT. ASICON 2019: 1-4 - [c12]Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang:
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model. ASICON 2019: 1-4 - [c11]Min Zhang, Peng Huang, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang:
FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network. ASICON 2019: 1-4 - [c10]Yachen Xiang, Peng Huang, Zheng Zhou, Runze Han, Yuning Jiang, Q. M. Shu, Zhiqiang Su, Yongbo Liu, Xiaoyan Liu, Jinfeng Kang:
Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation. ISCAS 2019: 1-4 - 2018
- [j1]Yuning Jiang
Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2726-2738 (2018) - [c9]Yun Li, K. L. Wang, Shaoyan Di, Peng Huang, Gang Du, Xiao-Yan Liu:
PBTI evaluation of In0.65Ga0.35As/In0.53Ga0.47As nanowire FETs with Al2O3 and LaAlO3 gate dielectrics. IRPS 2018: 7-1 - [c8]Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhekang Dong, Zhiqiang Su, Yongbo Liu, L. Liu, Xiaoyan Liu, Jinfeng Kang:
A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient. ISCAS 2018: 1-4 - 2016
- [c7]Jinfeng Kang, Peng Huang, Zhe Chen, Yudi Zhao, Chen Liu, Runze Han, Lifeng Liu, Xiaoyan Liu, Yangyuan Wang, Bin Gao:
Physical understanding and optimization of resistive switching characteristics in oxide-RRAM. ESSDERC 2016: 154-159 - [i1]Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong:
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays. CoRR abs/1606.07457 (2016) - 2015
- [c6]Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong:
Modeling and design optimization of ReRAM. ASP-DAC 2015: 576-581 - [c5]Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong:
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. DATE 2015: 1425-1430 - [c4]Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu
RRAM based synaptic devices for neuromorphic visual systems. DSP 2015: 1219-1222 - 2014
- [c3]Peng Huang, Bing Chen, Haitong Li
Parameters extraction on HfOX based RRAM. ESSDERC 2014: 250-253 - [c2]Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. ISCAS 2014: 417-420 - [c1]Shimeng Yu
Design guidelines for 3D RRAM cross-point architecture. ISCAS 2014: 421-424
Coauthor Index
aka: Xiao-Yan Liu
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