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Neiel Leyva
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2020 – today
- 2024
- [j2]Neiel Leyva
, Alireza Monemi, Noelia Oliete-Escuín
OpenPiton4HPC: Optimizing OpenPiton Toward High-Performance Manycores. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(3): 395-408 (2024) - 2023
- [c7]Max Doblas
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. DCIS 2023: 1-6 - [c6]Neiel Leyva
OpenPiton Optimizations Towards High Performance Manycores. NoCArc@MICRO 2023: 27-33 - 2022
- [j1]Neiel Leyva
SynFull-RTL: Evaluation Methodology for RTL NoC Designs. IEEE Des. Test 39(6): 58-69 (2022) - [c5]Guillem Cabo, Gerard Candón, Xavier Carril
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS 2022: 1-6 - [c4]Víctor Soria Pardos
Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI. DSD 2022: 254-261 - 2021
- [c3]Alireza Monemi, Iván Pérez, Neiel Leyva, Enrique Vallejo
PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip. NOCS 2021: 41-48 - 2020
- [c2]Jaume Abella
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS 2020: 1-6
2010 – 2019
- 2019
- [c1]Neiel I. Leyva-Santes, Ivan Perez, César-Alejandro Hernández-Calderón, Enrique Vallejo
Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. ISUM 2019: 237-248
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last updated on 2024-10-07 21:18 CEST by the dblp team
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