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Masaru Osada
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2020 – today
- 2024
- [j3]Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka:
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 746-750 (2024) - [j2]Masaru Osada
, Zule Xu
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59(7): 2171-2184 (2024) - 2023
- [c5]Zunsong Yang
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j1]Masaru Osada
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5072-5084 (2022) - [c4]Masaru Osada, Zule Xu, Tetsuya Iizuka:
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC 2022: 245-248 - [c3]Zunsong Yang
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits 2022: 10-11 - 2021
- [c2]Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits 2021: 1-2 - 2020
- [c1]Masaru Osada, Zule Xu, Tetsuya Iizuka:
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits 2020: 1-2
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