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Riccardo Scarsi
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2000 – 2009
- 2003
- [j8]Luca Benini, Alberto Macii
, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Scheduling battery usage in mobile systems. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1136-1143 (2003) - 2001
- [j7]Luca Benini, Giuliano Castelli, Alberto Macii
Battery-Driven Dynamic Power Management. IEEE Des. Test Comput. 18(2): 53-60 (2001) - [j6]Alberto Macii
Stream synthesis for efficient power simulation based on spectral transforms. IEEE Trans. Very Large Scale Integr. Syst. 9(3): 417-426 (2001) - [j5]Luca Benini, Giuliano Castelli, Alberto Macii
Discrete-time battery models for system-level low-power design. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 630-640 (2001) - [c11]Luca Benini, Giuliano Castelli, Alberto Macii
Extending lifetime of portable systems by battery scheduling. DATE 2001: 197-203 - 2000
- [j4]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 459-472 (2000) - [j3]Luca Benini, Alberto Macii
Architectures and synthesis algorithms for power-efficient businterfaces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 969-980 (2000) - [j2]Luca Benini, Giovanni De Micheli, Alberto Macii
Glitch power minimization by selective gate freezing. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 287-298 (2000) - [c10]Luca Benini, Giuliano Castelli, Alberto Macii
A Discrete-Time Battery Model for High-Level Power Estimation. DATE 2000: 35-39 - [c9]Andrea Acquaviva, Riccardo Scarsi:
A spatially-adaptive bus interface for low-switching communication (poster session). ISLPED 2000: 238-240 - [c8]Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi:
Battery-Driven Dynamic Power Management of Portable Systems. ISSS 2000: 25-33
1990 – 1999
- 1999
- [j1]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) - [c7]Luca Benini, Alberto Macii
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. DAC 1999: 128-133 - [c6]Luca Benini, Giovanni De Micheli, Alberto Macii
Glitch Power Minimization by Gate Freezing. DATE 1999: 163-167 - [c5]Alberto Macii
Regression-Based Macromodeling for Delay Estimation of Behavioral Components. Great Lakes Symposium on VLSI 1999: 188-191 - 1998
- [c4]Fabrizio Ferrandi
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. ICCAD 1998: 235-241 - [c3]Alberto Macii
Stream synthesis for efficient power simulation based on spectral transforms. ISLPED 1998: 30-35 - 1997
- [c2]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ED&TC 1997: 514-520 - [c1]Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Fast power estimation for deterministic input streams. ICCAD 1997: 494-501
Coauthor Index
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