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Tom J. Mannos
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2020 – today
- 2024
- [j5]Idris Somoye
, Jim Plusquellic
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. Cryptogr. 8(2): 16 (2024) - [j4]Idris Somoye
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1677-1690 (2024) - 2022
- [j3]Donald E. Owen, Jithin Joseph, Jim Plusquellic
Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor. Cryptogr. 6(3): 38 (2022) - [j2]Jim Plusquellic
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 438-451 (2022)
2010 – 2019
- 2019
- [j1]James Obert, Tom J. Mannos:
ASIC STA Path Verification Using Semi-Supervised Learning. Int. J. Semantic Comput. 13(2): 229-244 (2019) - [c2]Tom J. Mannos, Brian Dziki, Moslema Sharif:
Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation. FPGA 2019: 116 - 2018
- [c1]James Obert, Tom J. Mannos:
Semi-Supervised Learning and ASIC Path Verification. AI4I 2018: 1-4
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