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Shunsuke Fukami
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2020 – today
- 2023
- [i6]Shuvro Chowdhury, Andrea Grimaldi
, Navid Anjum Aadit, Shaila Niazi, Masoud Mohseni, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Luke Theogarajan, Giovanni Finocchio, Supriyo Datta, Kerem Yunus Çamsari
A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms. CoRR abs/2302.06457 (2023) - [i5]Keito Kobayashi, Nihal Singh, Qixuan Cao, Kemal Selcuk, Tianrui Hu, Shaila Niazi, Navid Anjum Aadit, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Kerem Yunus Çamsari:
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning. CoRR abs/2304.05949 (2023) - [i4]Kemal Selcuk, Shun Kanai, Rikuto Ota, Hideo Ohno, Shunsuke Fukami, Kerem Yunus Çamsari:
Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets. CoRR abs/2311.06642 (2023) - 2021
- [j3]Masanori Natsui
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - [i3]Jan Kaiser
Hardware-aware in-situ Boltzmann machine learning using stochastic magnetic tunnel junctions. CoRR abs/2102.05137 (2021) - [i2]Qiming Shao, Zhongrui Wang, Yan Zhou, Shunsuke Fukami, Damien Querlioz, J. Joshua Yang, Yiran Chen, Leon O. Chua:
Spintronic memristors for computing. CoRR abs/2112.02879 (2021) - 2020
- [c7]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2 - [i1]Kerem Yunus Çamsari, Mustafa Mert Torunbalci, William A. Borders, Hideo Ohno, Shunsuke Fukami:
Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits. CoRR abs/2012.06950 (2020)
2010 – 2019
- 2019
- [j2]William A. Borders, Ahmed Zeeshan Pervaiz, Shunsuke Fukami
Integer factorization using stochastic magnetic tunnel junctions. Nat. 573(7774): 390-393 (2019) - 2015
- [c6]Daisuke Suzuki, Masanori Natsui
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - 2014
- [c5]Shunsuke Fukami
Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. ASP-DAC 2014: 684-691 - [c4]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c3]Noboru Sakimura, Yukihide Tsuji
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - 2012
- [c2]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974
2000 – 2009
- 2009
- [c1]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami
A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC 2009: 462-463 - 2007
- [j1]Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42(11): 2378-2385 (2007)
Coauthor Index
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