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David Mahashin
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2020 – today
- 2023
- [c6]Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans:
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. ISSCC 2023: 204-205 - 2021
- [j2]Jay Im
, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. IEEE J. Solid State Circuits 56(1): 7-18 (2021) - 2020
- [j1]Mayank Raj
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE J. Solid State Circuits 55(4): 1086-1095 (2020) - [c5]Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. ECOC 2020: 1-4 - [c4]Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. ISSCC 2020: 116-118
2010 – 2019
- 2019
- [c3]Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. VLSI Circuits 2019: 190- - 2018
- [c2]James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48 - [c1]Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. VLSI Circuits 2018: 145-146
Coauthor Index
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