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Yong-Un Jeong
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- affiliation: Seoul National University, South Korea
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2020 – today
- 2024
- [j13]Jaekwang Yun
, Sang-Yoon Lee
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces. IEEE J. Solid State Circuits 59(9): 2971-2982 (2024) - [j12]Shin-Hyun Jeong, Yong-Un Jeong, Suhwan Kim:
An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4628-4632 (2024) - [c6]Sanghyuk Seo, Yong-Un Jeong, Jaekwang Yun, Jaewook Kim, Suhwan Kim:
A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces. ISCAS 2024: 1-5 - 2023
- [j11]Yong-Un Jeong
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces. IEEE J. Solid State Circuits 58(9): 2659-2667 (2023) - [j10]Yong-Un Jeong
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4793-4803 (2023) - 2022
- [j9]Joo-Hyung Chae
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters. IEEE Access 10: 37446-37456 (2022) - [j8]Hyunkyu Park
A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces. IEEE Access 10: 91888-91896 (2022) - [j7]Yong-Un Jeong
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1125-1134 (2022) - [j6]Sangyoon Lee
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4208-4212 (2022) - 2021
- [j5]Sungphil Choi
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. IEEE Access 9: 120285-120296 (2021) - [j4]Yong-Un Jeong
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. IEEE J. Solid State Circuits 56(4): 1278-1287 (2021) - [c5]Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae:
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. ISCAS 2021: 1-5 - 2020
- [j3]Yong-Un Jeong
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1589-1593 (2020) - [j2]Joo-Hyung Chae
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 2972-2983 (2020) - [c4]Jaekwang Yun
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. A-SSCC 2020: 1-4 - [c3]Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Suhwan Kim:
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c2]Yong-Un Jeong, Joo-Hyung Chae
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. ISLPED 2019: 1-6 - 2018
- [j1]Jihwan Park, Joo-Hyung Chae
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface. IEEE J. Solid State Circuits 53(10): 2878-2888 (2018) - 2017
- [c1]Jihwan Park, Joo-Hyung Chae
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface. A-SSCC 2017: 257-260
Coauthor Index
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