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James A. Kahle
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- affiliation: IBM Systems and Technology Group, Austin, TX, USA
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2020 – today
- 2023
- [c11]Christoph Hagleitner, Florian Auernhammer, James C. Sexton, Constantinos Evangelinos, Guerney Hunt, Christian Pinto, Michael Johnston, Charles R. Johns, Jim Kahle:
An Architecture for Heterogeneous High-Performance Computing Systems: Motivation and Requirements. JVA 2023: 14 - 2021
- [c10]Christoph Hagleitner, Dionysios Diamantopoulos, Burkhard Ringlein
, Constantinos Evangelinos, Charles R. Johns, Rong N. Chang
Heterogeneous Computing Systems for Complex Scientific Discovery Workflows. DATE 2021: 13-18
2010 – 2019
- 2019
- [c9]James A. Kahle, Jaime Moreno, Daniel Dreps:
Summit and Sierra: Designing AI/HPC Supercomputers. ISSCC 2019: 42-43 - 2018
- [c8]Sudharshan S. Vazhkudai, Bronis R. de Supinski, Arthur S. Bland, Al Geist, James C. Sexton, Jim Kahle, Christopher Zimmer, Scott Atchley, Sarp Oral, Don E. Maxwell, Verónica G. Vergara Larrea, Adam Bertsch, Robin Goldstone, Wayne Joubert, Chris Chambreau, David Appelhans, Robert Blackmore, Ben Casses, George Chochia, Gene Davison, Matthew A. Ezell, Tom Gooding, Elsa Gonsiorowski, Leopold Grinberg, Bill Hanson, Bill Hartner, Ian Karlin, Matthew L. Leininger, Dustin Leverman, Chris Marroquin, Adam Moody, Martin Ohmacht, Ramesh Pankajakshan, Fernando Pizzano, James H. Rogers, Bryan S. Rosenburg, Drew Schmidt, Mallikarjun Shankar, Feiyi Wang, Py Watson, Bob Walkup, Lance D. Weems, Junqi Yin:
The design, deployment, and evaluation of the CORAL pre-exascale systems. SC 2018: 52:1-52:12 - 2011
- [j4]Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46(1): 145-161 (2011) - 2010
- [c7]Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban:
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103
2000 – 2009
- 2007
- [c6]Jim Kahle:
Cell architecture: key physical design features and methodology. ISPD 2007: 1 - 2006
- [j3]Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006) - [c5]Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel:
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC 2006: 871-878 - 2005
- [j2]James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy:
Introduction to the Cell multiprocessor. IBM J. Res. Dev. 49(4-5): 589-604 (2005) - [c4]Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC 2005: 45-49 - [c3]James A. Kahle:
The Cell Processor Architecture. MICRO 2005: 3
1990 – 1999
- 1994
- [j1]Gianfranco Gerosa, Sonya Gary, Carl Dietz, Dac Pham, Kathy Hoover, Jose Alvarez, Hector Sanchez, Pete Ippolito, Tai Ngo, Suzanne Litch, Jim Eno, Jim Golab, Neil Vanderschaaf, Jim Kahle:
A 2.2 W, 80 MHz superscalar RISC microprocessor. IEEE J. Solid State Circuits 29(12): 1440-1454 (1994) - 1990
- [c2]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. Compcon 1990: 173-178
1980 – 1989
- 1989
- [c1]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. ICCD 1989: 138-142
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