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Gyeong-Gu Kang

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affiliation: KAIST, South Korea

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2020 – today

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2024
[j5]
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Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim:
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer. IEEE J. Solid State Circuits 59(4): 1050-1066 (2024)
[j4]
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Yousung Park, Gyeong-Gu Kang, Gyu-Wan Lim, Seunghwa Shin, Yong-Sung Ahn, Wonyoun Kim, Hyun-Sik Kim:
A 10-bit Source-Driver IC With Charge-Modulation DAC for Enhanced Frame-Rate Mobile OLED Displays. IEEE J. Solid State Circuits 59(11): 3511-3524 (2024)
[c17]
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Yousung Park, Gyeong-Gu Kang, Gyu-Wan Lim, Seunghwa Shin, Yong-Sung Ahn, Wonyoun Kim, Hyun-Sik Kim:
26.1 A 600ch 10b Source-Driver IC with a Charge-Modulation DAC Achieving 1-Horizontal Time of 1.5μs Suitable for 240Hz-Frame-Rate Mobile Displays. ISSCC 2024: 432-434
[c16]
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Gyu-Wan Lim, Gyeong-Gu Kang, Seunghwa Shin, Kihyun Kim, Yousung Park, Won Kim, Young-Bok Kim, Hyun-Kyu Jeon, Hyun-Sik Kim:
An OLED Display Driver IC Embedding -63dB CMR, 80mV/nA Sensitivity, 390pA Detectable, and Column-Parallel Pixel Current Readout for Real-Time Non-Uniformity Compensation. VLSI Technology and Circuits 2024: 1-2
2023
[j3]
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Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim:
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays. IEEE J. Solid State Circuits 58(11): 3164-3178 (2023)
[c15]
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Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim:
A Mobile OLED Source-Driver IC featuring Ultra-Compact 3-Stage-Cascaded 10-Bit DAC and 42V/μs-Slew-Rate True-DC-Interpolative Super-OTA Buffer. VLSI Technology and Circuits 2023: 1-2
2022
[j2]
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Jiho Lee, Sang-Han Lee, Gyeong-Gu Kang, Jae-Hyun Kim, Gyu-Hyeong Cho, Hyun-Sik Kim:
A Triboelectric Energy-Harvesting Interface With Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Techniques. IEEE J. Solid State Circuits 57(12): 3825-3839 (2022)
[c14]
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Woojin Jang, Gyeong-Gu Kang, Yong Lim, Hyun-Sik Kim:
A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity. ESSCIRC 2022: 317-320
[c13]
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Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim:
A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm²/channel and 4.8mV DVO for Mobile OLED Displays. ISSCC 2022: 110-112
[c12]
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Jiho Lee, Sang-Han Lee, Gyeong-Gu Kang, Jae-Hyun Kim, Gyu-Hyeong Cho, Hyun-Sik Kim:
A 130V Triboelectric Energy-Harvesting Interface in .18µm BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique. ISSCC 2022: 474-476
[c11]
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Gyeong-Gu Kang, Ji-Hun Lee, Se-Un Shin, Gyu-Hyeong Cho, Hyun-Sik Kim:
A 5.6W-Power 96.6%-Efficiency Boost-Oriented SIDO Step-Up/Down DC-DC Converter Embedding Buck Conversion with an Energy-Balancing Capacitor. VLSI Technology and Circuits 2022: 180-181
[c10]
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Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim:
A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode. VLSI Technology and Circuits 2022: 182-183
[c9]
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Hong-Hyun Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyun-Sik Kim:
A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull Technique. VLSI Technology and Circuits 2022: 194-195
2021
[j1]
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Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim:
A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. IEEE J. Solid State Circuits 56(12): 3593-3607 (2021)
[c8]
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Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyun-Ki Han, Hyun-Sik Kim:
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique. ISSCC 2021: 86-88
[c7]
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Gyeong-Gu Kang, Seok-Tae Koh, Woojin Jang, Jiho Lee, Seongjoo Lee, Ohjo Kwon, Keumdong Jung, Hyun-Sik Kim:
A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier. VLSI Circuits 2021: 1-2
[c6]
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Jae-Young Ko, Yeunhee Huh, Min-Woo Ko, Gyeong-Gu Kang, Gyu-Hyeong Cho, Hyun-Sik Kim:
A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs. VLSI Circuits 2021: 1-2
[c5]
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Hongseok Shin, Doojin Jang, Gyeong-Gu Kang, Jinuk Kim, Chul Kim, Sohmyung Ha, Minkyu Je:
A 96.6%-Efficiency Continuous-Input-Current Hybrid Dual-Path Buck-Boost Converter with Single-Mode Operation and Non-Stopping Output Current Delivery. VLSI Circuits 2021: 1-2
2020
[c4]
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  - conf/isscc/KoKKLKKKLCSCK20
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Min-Woo Ko, Gyeong-Gu Kang, Ki-Duk Kim, Ji-Hun Lee, Seok-Tae Koh, Tae-Hwang Kong, Sang-Ho Kim, Sungyong Lee, Michael Choi, Jongshin Shin, Gyu-Hyeong Cho, Hyunsik Kim:
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries. ISSCC 2020: 204-206
[c3]
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Ji-Hun Lee, Gyeong-Gu Kang, Min-Woo Ko, Gyu-Hyeong Cho, Hyun-Sik Kim:
An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA. VLSI Circuits 2020: 1-2

2010 – 2019

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2018
[c2]
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Kiduk Kim, Seunghyun Park, Kye-Seok Yoon, Gyeong-Gu Kang, Hyun-Ki Han, Ji-Su Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee, Hyunsik Kim, Kwyro Lee, Gyu-Hyeong Cho:
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm² 1.89μVrms noise 12b biasing DAC. ISSCC 2018: 192-194
[c1]
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Min-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-Un Shin, Hyun-Ki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sang-Jin Lim, Se-Hong Park, Hyung-Min Lee, Gyu-Hyeong Cho:
A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management. ISSCC 2018: 428-430

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