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Chengning Wang
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2020 – today
- 2024
- [c10]Chengning Wang, Dan Feng, Yuchong Hu, Wei Tong, Jingning Liu:
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM. DAC 2024: 27:1-27:6 - 2023
- [j9]Wei Zhao
, Jie Xu, Xueliang Wei
A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 122-135 (2023) - [j8]Wei Zhao
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3840-3853 (2023) - [c9]Chengning Wang, Dan Feng, Wei Tong, Jingning Liu:
CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays. DAC 2023: 1-6 - [c8]Jinpeng Liu, Wei Tong, Bing Wu, Huan Cheng, Chengning Wang:
ICON: An IR Drop Compensation Method at OU Granularity with Low Overhead for eNVM-based Accelerators. ICCD 2023: 102-109 - 2022
- [j7]Chengning Wang
Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3479-3491 (2022) - 2021
- [j6]Yang Zhang
EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture. IEEE Access 9: 167173-167189 (2021) - [j5]Chengning Wang
Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage. IEEE Trans. Computers 70(4): 566-580 (2021) - [j4]Chengning Wang
Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 762-775 (2021) - [c7]Wei Zhao, Wei Tong, Dan Feng, Jingning Liu, Zhangyu Chen, Jie Xu, Bing Wu, Chengning Wang
Improving the energy efficiency of STT-MRAM based approximate cache. DATE 2021: 1104-1109 - 2020
- [j3]Bing Wu
A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1806-1819 (2020) - [c6]Xueliang Wei, Dan Feng, Wei Tong, Jingning Liu, Chengning Wang, Liuqing Ye:
CCHL: Compression-Consolidation Hardware Logging for Efficient Failure-Atomic Persistent Memory Updates. ICPP 2020: 12:1-12:11
2010 – 2019
- 2019
- [j2]Chengning Wang
Cross-point Resistive Memory: Nonideal Properties and Solutions. ACM Trans. Design Autom. Electr. Syst. 24(4): 46:1-46:37 (2019) - [c5]Bing Wu
ReRAM Crossbar-Based Analog Computing Architecture for Naive Bayesian Engine. ICCD 2019: 147-155 - [c4]Yang Zhang
Tiered-ReRAM: A Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture. MSST 2019: 92-102 - 2018
- [j1]Yang Zhang
CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System. ACM Trans. Archit. Code Optim. 15(2): 22:1-22:26 (2018) - [c3]Bing Wu
Aliens: a novel hybrid architecture for resistive random-access memory. ICCAD 2018: 54 - [c2]Yang Zhang
Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 330-337 - 2017
- [c1]Chengning Wang
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory. ICCD 2017: 281-288
Coauthor Index
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