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Rafael S. Ferreira
Person information
- affiliation: Catholic University of Pelotas, Graduate Program on Electronic Engineering and Computing, Porto Alegre, Brazil
Other persons with the same name
- Rafael Ferreira — disambiguation page
- Rafael Ferreira Leite de Mello
(aka: Rafael Ferreira Mello, Rafael Fe Mello, Rafael Ferreira 0002) — Rural Federal University of Pernambuco, Recife, Brazil
- Rafael Ferreira 0003
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2020 – today
- 2024
- [c13]Ramiro Viana, Fernando Sagrilo, Rafael S. Ferreira, Marta Loose, Marcelo Schiavon Porto, Guilherme Corrêa, Luciano Agostini:
A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning. LASCAS 2024: 1-5 - [c12]Ramiro Viana, Marta Loose, Rafael S. Ferreira, Marcelo Schiavon Porto, Guilherme Corrêa, Luciano Agostini:
A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees. SBCCI 2024: 1-5 - 2023
- [c11]Rafael S. Ferreira, Luciano Agostini, Cláudio Machado Diniz, Bruno Zatt:
Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding. SBCCI 2023: 1-6 - 2022
- [j1]Bianca Silveira, Guilherme Paim
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. Circuits Syst. Signal Process. 41(3): 1577-1595 (2022) - [c10]Rafael S. Ferreira, Lucas Santos, Luciano Agostini, Cláudio Machado Diniz, Bruno Zatt:
VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis. ICECS 2022 2022: 1-4
2010 – 2019
- 2019
- [c9]Rafael Ferreira, Mateus Leme, Marcel Moscarelli Corrêa, Luciano Agostini, Cláudio Machado Diniz, Bruno Zatt:
Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators. ICECS 2019: 426-429 - [c8]Rafael S. Ferreira, Guilherme Paim
HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. MWSCAS 2019: 331-334 - 2017
- [c7]Leandro M. G. Rocha
Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers. ICECS 2017: 478-481 - [c6]Bianca Silveira, Brunno Abreu, Guilherme Paim
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding. ICECS 2017: 490-493 - [c5]Leandro M. G. Rocha
Physical implementation of an ASIC-oriented SRAM-based viterbi decoder. ICECS 2017: 526-529 - [c4]Rafael Ferreira, Bianca Silveira, Mateus Beck Fonseca, Cláudio Machado Diniz, Eduardo A. C. da Costa
Low power sum of absolute differences architecture using novel hybrid adder. LASCAS 2017: 1-4 - [c3]Guilherme Paim
Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform. NEWCAS 2017: 25-28 - [c2]Bianca Silveira, Rafael S. Ferreira, Guilherme Paim
Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors. NEWCAS 2017: 277-280 - [c1]Guilherme Paim
A power-predictive environment for fast and power-aware ASIC-based FIR filter design. SBCCI 2017: 168-173
Coauthor Index
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