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Annajirao Garimella
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2010 – 2019
- 2018
- [c13]Punith R. Surkanti, Annajirao Garimella, Paul M. Furth:
Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview. VLSID 2018: 232-237 - 2017
- [c12]Punith R. Surkanti, Annajirao Garimella, Mahender Manda, Paul M. Furth:
On the analysis of low output impedance characteristic of flipped voltage follower (FVF) and FVF LDOs. MWSCAS 2017: 17-20 - 2015
- [c11]Sri Harsh Pakala, Mahender Manda, Punith R. Surkanti, Annajirao Garimella, Paul M. Furth:
Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp. MWSCAS 2015: 1-4 - 2012
- [c10]Paul M. Furth, Sri Harsh Pakala, Annajirao Garimella, Chaitanya Mohan:
A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation. CICC 2012: 1-4 - [c9]Paul M. Furth, Nitya R. Thota, Venkat Harish Nammi, Annajirao Garimella:
Low dropout (LDO) voltage regulator design using split-length compensation. MWSCAS 2012: 1088-1091 - [c8]Annajirao Garimella, Punith R. Surkanti, Paul M. Furth:
Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. VLSI Design 2012: 31-32 - [c7]Annajirao Garimella, Punith R. Surkanti, Paul M. Furth:
Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. VLSI Design 2012: 131-136 - 2010
- [j1]Annajirao Garimella, M. Wasequr Rashid
, Paul M. Furth:
Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 250-254 (2010) - [c6]Annajirao Garimella, M. Wasequr Rashid
Single Miller compensation using inverting current buffer for multi-stage amplifiers. ISCAS 2010: 1579-1582
2000 – 2009
- 2009
- [c5]Annajirao Garimella, Paul M. Furth:
A 1.21V, 100mA, 0.1µF-10µF output capacitor low drop-out voltage regulator for SoC applications. ICECS 2009: 375-378 - 2008
- [c4]Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín
An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. VLSI Design 2008: 294-299 - 2007
- [c3]Jaime Ramírez-Angulo, Annajirao Garimella, Lalitha Mohana Kalyani-Garimella, Milind S. Sawant, Antonio Lopez-Martin
Low voltage gain boosting schemes for one stage operational amplifiers. ECCTD 2007: 531-534 - 2006
- [c2]Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal
Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs. CICC 2006: 1-4 - 2003
- [c1]Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan:
VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. VLSI Design 2003: 283-
Coauthor Index
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