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Yoshiji Kobayashi
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1990 – 1999
- 1998
- [j6]Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino:
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33(10): 1536-1544 (1998) - 1997
- [j5]Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino:
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. IEEE J. Solid State Circuits 32(2): 215-221 (1997) - 1995
- [j4]Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi:
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. IEEE J. Solid State Circuits 30(1): 19-24 (1995) - [j3]Noboru Ishihara, Shuichi Fujita, Minoru Togashi, Shigeki Hino, Yoshimitsu Arai, Nobuyuki Tanaka, Yoshiji Kobayashi, Yukio Akazawa:
3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections. IEEE J. Solid State Circuits 30(12): 1493-1501 (1995) - 1994
- [j2]Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi:
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. IEEE J. Solid State Circuits 29(5): 546-550 (1994)
1980 – 1989
- 1986
- [j1]Yousuke Yamamoto, Hiroshi Miyanaga, Yoshiji Kobayashi, Yasukazu Terada, Naoaki Yamanaka:
A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit. IEEE Trans. Commun. 34(9): 953-955 (1986)
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