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Cheng-Ru Ho
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2020 – today
- 2024
- [c9]J. Q. Wang, Amber Tan, Amrutha Iyer, A. Fan, A. Farhoodfar, B. Alnabulsi, B. Smith, Chang-Feng Loi, Cheng-Ru Ho, D. Cartina, Jamal Riani, J. Casanova, Karthik Raviprakash, L. Patra
, Luke Wang, M. Bachu, Sagar Ray, Sau Siong Chong, S. Dallaire, The Linh Nguyen, Tzu-Fan Wu, Vishal Giridharan, V. Gurumoorthy, X. Ding, Y. Yin, Zhuochao Sun, Steve Jantzi, Lawrence Tse:
7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET. ISSCC 2024: 123-125 - 2023
- [c8]Arik Zafrany, Daniel Burgos, Li Cai, Sau Siong Chong, Colin Cramm, Sadegh Dadash, Vishal Giridharan, Vivek Gurumoorthy, Belal Helal, Cheng-Ru Ho, Amrutha Iyer, Steve Jantzi, Chang-Feng Loi, The Linh Nguyen, Kevin Parker, Ed Pillai, Karthik Raviprakash, Sagar Ray, Paolo Rossi, Zhuochao Sun, Amber Tan, Lawrence Tse, Brian Wall, Luke Wang, Jeffrey Wang, Tzu-Fan Wu:
A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers. OFC 2023: 1-3 - 2022
- [j4]Qiaochu Zhang
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57(1): 80-89 (2022) - 2021
- [c7]P. Mishra, A. Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, M. Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou:
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. ISSCC 2021: 138-140 - [c6]Qiaochu Zhang
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC 2021: 410-412
2010 – 2019
- 2018
- [c5]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. ISSCC 2018: 254-256 - [c4]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC 2018: 394-396 - 2017
- [j3]Tzu-Fan Wu
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. IEEE J. Solid State Circuits 52(9): 2335-2349 (2017) - 2016
- [j2]Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 3216-3230 (2016) - [j1]Cheng-Ru Ho
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1111-1122 (2016) - [c3]Cheng-Ru Ho, Mike Shuo-Wei Chen:
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. ESSCIRC 2016: 213-216 - [c2]Cheng-Ru Ho, Mike Shuo-Wei Chen:
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. ISSCC 2016: 190-191 - 2015
- [c1]Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. CICC 2015: 1-4
Coauthor Index
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