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Min-Seong Choo
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2020 – today
- 2024
- [j11]Chan-Ho Kye, Yu-Jin Byeon, Kyojin Choo, Min-Seong Choo:
Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4973-4984 (2024) - [j10]Gijin Park
, Sun-Ho Yeom, InWoo Jang
3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4091-4095 (2024) - [j9]Jihun Choi, Sangwook Na, Hojin Kim, Hyungdong Roh, Youngjae Cho, Michael Choi, Min-Seong Choo, Jeongjin Roh:
High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4613-4617 (2024) - [c12]Dong-Hoe Heo, Tae-Hyeon Kim, Kwang-Ho Lee, Min-Seong Choo:
An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery. ICEIC 2024: 1-4 - [c11]Seung-Mo Jin, Shin-Uk Kang, Min-Seong Choo:
Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks. ICEIC 2024: 1-2 - [c10]Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo:
Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application. ICEIC 2024: 1-2 - 2023
- [j8]Dongjun Lee
An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. IEEE Access 11: 7530-7539 (2023) - [c9]InWoo Jang
Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter. ICEIC 2023: 1-2 - [c8]Shin-Uk Kang, Jin-Woo Han, Min-Seong Choo:
Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application. ICEIC 2023: 1-4 - 2022
- [c7]Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC 2022: 249-252 - 2021
- [j7]Kwanseo Park
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56(5): 1597-1607 (2021) - [j6]Min-Seong Choo
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021)
2010 – 2019
- 2019
- [j5]Min-Seong Choo
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j4]Min-Seong Choo
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c6]Minho Choi, Chan-Ho Kye, Jonghyun Oh
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time. ISSCC 2019: 432-434 - [c5]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits 2019: 194- - 2018
- [j3]Sung-Yong Cho
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j2]Min-Seong Choo
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1819-1823 (2018) - [c4]Min-Seong Choo
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC 2018: 73-76 - 2017
- [j1]Kwanseo Park
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1432-1436 (2017) - [c3]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495 - 2016
- [c2]Jinhyung Lee, Sungwoo Kim, Min-Seong Choo
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS 2016: 1662-1665 - 2015
- [c1]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387
Coauthor Index
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